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? 2011 microchip technology inc. ds39995b pic24fv32ka304 data sheet 20/28/44/48-pin, general purpose, 16-bit flash microcontrollers with xlp technology
ds39995b-page 2 ? 2011 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-079-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2011 microchip technology inc. ds39995b-page 3 pic24fv32ka304 family power management modes: ? run ? cpu, flash, sram and peripherals on ? doze ? cpu clock runs slower than peripherals ? idle ? cpu off, flash, sram and peripherals on ? sleep ? cpu, flash and peripherals off and sram on ? deep sleep ? cpu, flash, sram and most peripherals off; multiple autonomous wake-up sources ? low-power consumption: - run mode currents down to 8 a, typical - idle mode currents down to 2.2 a, typical - deep sleep mode currents down to 20 na, typical - real-time clock/calendar currents down to 700 na, 32 khz, 1.8v - watchdog timer 500 na, 1.8v typical high-performance cpu: ? modified harvard architecture ? up to 16 mips operation @ 32 mhz ? 8 mhz internal oscillator with 4x pll option and multiple divide options ? 17-bit by 17-bit single-cycle hardware multiplier ? 32-bit by 16-bit hardware divider 16-bit x 16-bit working register array ? c compiler optimized instruction set architecture peripheral features: ? hardware real-time clock and calendar (rtcc): - provides clock, calendar and alarm functions - can run in deep sleep mode - can use 50/60 hz power line input as clock source ? programmable 32-bit cyclic redundancy check (crc) ? multiple serial communication modules: - two 3-/4-wire spi modules -two i 2 c? modules with multi-master/slave support - two uart modules supporting rs-485, rs-232, lin/j2602, irda ? ? five 16-bit timers/counters with programmable prescaler: - can be paired as 32-bit timers/counters ? three 16-bit capture inputs with dedicated timers ? three 16-bit compare/pwm output with dedicated timers ? configurable open-drain outputs on digital i/o pins ? up to three external interrupt sources analog features: ? 12-bit, up to 16-channel analog-to-digital converter: - 100 ksps conversion rate - conversion available during sleep and idle - auto-sampling timer-based option for sleep and idle modes - wake on auto-compare option ? dual rail-to-rail analog comparators with programmable input/output configuration ? on-chip voltage reference ? internal temperature sensor ? charge time measurement unit (ctmu): - used for capacitance sensing, 16 channels - time measurement, down to 200 ps resolution - delay/pulse generation, down to 1 ns resolution special microcontroller features: ? wide operating voltage range: - 1.8v to 3.6v (pic24f devices) - 2.0v to 5.5v (pic24fv devices) ? low power wake-up sources and supervisors: - ultra-low power wake-up (ulpwu) for sleep/deep sleep - low-power watchdog timer (dswdt) for deep sleep - extreme low-power brown-out reset (dsbor) for deep sleep, lpbor for all other modes ? system frequency range declaration bits: - declaring the frequency range optimizes the current consumption. ? standard watchdog timer (wdt) with on-chip, low-power rc oscillator for reliable operation ? programmable high/low-voltage detect (hlvd) ? standard brown-out reset (bor) with 3 programmable trip points that can be disabled in sleep ? high-current sink/source (18 ma/18 ma) on all i/o pins ? flash program memory: - erase/write cycles: 10,000 minimum - 40 years? data retention minimum ? data eeprom: - erase/write cycles: 100,000 minimum - 40 years? data retention minimum ? fail-safe clock monitor ? programmable reference clock output ? self-programmable under software control ? in-circuit serial programming? (icsp?) and in-circuit debug (icd) via 2 pins 20/28/44/48-pin, general purpose, 16-bit flash microcontrollers with xlp technology
pic24fv32ka304 family ds39995b-page 4 ? 2011 microchip technology inc. pic24f device pins memory timers 16-bit capture input compare/pwm output uart w/ irda ? spi i 2 c? 12-bit a/d (ch) comparators ctmu (ch) rtcc flash program (bytes) sram (bytes) ee data (bytes) pic24fv16ka301 /pic24f16ka301 2016k 2k51253322212312y pic24fv32ka301 /pic24f32ka301 2032k 2k51253322212312y pic24fv16ka302 /pic24f16ka302 2816k 2k51253322213313y pic24fv32ka302 /pic24f32ka302 2832k 2k51253322213313y pic24fv16ka304 /pic24f16ka304 4416k 2k51253322216316y pic24fv32ka304 /pic24f32ka304 4432k 2k51253322216316y
? 2011 microchip technology inc. ds39995b-page 5 pic24fv32ka304 family pin diagrams legend: pin numbers in bold indicate pin function differences between pic24fv and pic24f devices. note 1: pic24f32ka304 device pins have a maximum voltage of 3.6v and are not 5v tolerant. 20-pin spdip/ssop/soic (1) 24fvxxka301 mclr /ra5 ra3 ra0 ra1 v dd v ss rb0 rb7 ra4 rb4 rb8 ra2 rb2 rb1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 rb15 rb14 rb13 rb12 rb9 ra6 or v cap pin pin features pic24fvxxka301 pic24fxxka301 1mclr /v pp /ra5 mclr /v pp /ra5 2pgec2/v ref +/cv ref +/an0/c3inc/sck2/cn2/ra0 pgec2/v ref +/cv ref +/an0/c3inc/sck2/cn2/ra0 3pged2/cv ref -/v ref -/an1/sdo2/cn3/ra1 pged2/cv ref -/v ref -/an1/sdo2/cn3/ra1 4 pged1/an2/ulpwu/ctcmp/c1ind/c2inb/c3ind/u2tx/sdi2/ oc2/cn4/rb0 pged1/an2/ulpwu/ctcmp/c1i nd/c2inb/c3ind/u2tx/sdi2/ oc2/cn4/rb0 5 pgec1/an3/c1inc/c2ina/u2rx/oc3/cted12/cn5/rb1 pgec1/an3/c1inc/c2ina/u2rx/oc3/cted12/cn5/rb1 6 an4/sda2/t5ck/t4ck/u1rx/cted13/cn6/rb2 an4/sda2/t5ck/t4ck/u1rx/cted13/cn6/rb2 7 osci/an13/c1inb/c2ind/clki/cn30/ra2 o sci/an13/c1inb/c2ind/clki/cn30/ra2 8 osco/an14/c1ina/c2inc/clko/cn29/ra3 osco/an14/c1ina/c2inc/clko/cn29/ra3 9 pged3/sosci/an15/u2rts /cn1/rb4 pged3/sosci/an15/u2rts /cn1/rb4 10 pgec3/sosco/sclki/u2cts /cn0/ra4 pgec3/sosco/sclki/u2cts /cn0/ra4 11 u1tx/c2out/oc1/ic1/cted1/int0/cn23/rb7 u1tx/int0/cn23/rb7 12 scl1/u1cts /c3out/cted10/cn22/rb8 scl1/u1cts /c3out/cted10/cn22/rb8 13 sda1/t1ck/u1rts /ic2/cted4/cn21/rb9 sda1/t1ck/u1rts /ic2/cted4/cn21/rb9 14 v cap c2out/oc1/ic1/cted1/int2/cn8/ra6 15 an12/lvdin/sck1/ss2 /ic3/cted2/int2/cn14/rb12 an12/lvdin/sck1/ss2/ic3/cted2/cn14/rb12 16 an11/sdo1/ocfb/ctpls/cn13/rb13 an11/sdo1/ocfb/ctpls/cn13/rb13 17 cv ref /an10/c3inb/rtcc/sdi1/c1out/ocfa/cted5/ int1/ cn12/rb14 cv ref /an10/c3inb/rtcc/sdi1/c1out/ocfa/cted5/ int1/ cn12/rb14 18 an9/c3ina/scl2/t3ck/t2ck/refo/ss1 /cted6/cn11/rb15 an9/c3ina/scl2/t3ck/t2ck/refo/ss1 /cted6/cn11/rb15 19 v ss /av ss v ss /av ss 20 v dd /av dd v dd /av dd 24fxxka301
pic24fv32ka304 family ds39995b-page 6 ? 2011 microchip technology inc. pin diagrams 28-pin spdip/ssop/soic (1,2) pic24fvxxka302 mclr /ra5 v ss v dd ra0 ra1 v dd v ss rb0 rb6 ra4 rb4 ra7 ra3 ra2 ra6 or v cap rb7 rb9 rb8 rb3 rb2 rb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rb15 rb14 rb13 rb12 rb10 rb11 rb5 pin pin features pic24fvxxka302 pic24fxxka302 1mclr /v pp /ra5 mclr /v pp /ra5 2v ref +/cv ref +/an0/c3inc/cted1/cn2/ra0 v ref +/cv ref +/an0/c3inc/cted1/cn2/ra0 3cv ref -/v ref -/an1/cn3/ra1 cv ref -/v ref -/an1/cn3/ra1 4 pged1/an2/ulpwu/ctcmp/c1ind/c2inb/c3ind/u2tx/cn4/rb0 pged1/an2/ulpwu/ctcmp/c1ind/c2inb/c3ind/u2tx/cn4/rb0 5 pgec1/an3/c1inc/c2ina/u2rx/cted12/cn5/rb1 pgec1/an3/c1inc/c2ina/u2rx/cted12/cn5/rb1 6 an4/c1inb/c2ind/sda2/t5ck/t4ck/u1rx/cted13/cn6/rb2 an4/c1inb/c2ind/sda2/t5ck/t4ck/u1rx/cted13/cn6/rb2 7 an5/c1ina/c2inc/scl2/cn7/rb3 an5/c1ina/c2inc/scl2/cn7/rb3 8v ss v ss 9 osci/an13/clki/cn30/ra2 osci/an13/clki/cn30/ra2 10 osco/an14/clko/cn29/ra3 osco/an14/clko/cn29/ra3 11 sosci/an15/u2rts /cn1/rb4 sosci/an15/u2rts /cn1/rb4 12 sosco/sclki/u2cts /cn0/ra4 sosco/sclki/u2cts /cn0/ra4 13 v dd v dd 14 pged3/asda (1) /sck2/cn27/rb5 pged3/asda (1) /sck2/cn27/rb5 15 pgec3/ascl (1) /sdo2/cn24/rb6 pgec3/ascl (1) /sdo2/cn24/rb6 16 u1tx/c2out/oc1/int0/cn23/rb7 u1tx/int0/cn23/rb7 17 scl1/u1cts /c3out/cted10/cn22/rb8 scl1/u1cts /c3out/cted10/cn22/rb8 18 sda1/t1ck/u1rts /ic2/cted4/cn21/rb9 sda1/t1ck/u1rts /ic2/cted4/cn21/rb9 19 sdi2/ic1/cted3/cn9/ra7 sdi2/ic1/cted3/cn9/ra7 20 v cap c2out/oc1/cted1/int2/cn8/ra6 21 pged2/sdi1/oc3/cted11/cn16/rb10 pged2/sdi1/oc3/cted11/cn16/rb10 22 pgec2/sck1/oc2/cted9/cn15/rb11 pgec2/sck1/oc2/cted9/cn15/rb11 23 an12/lvdin/ss2 /ic3/cted2/int2/cn14/rb12 an12/lvdin/ss2 /ic3/cted2/cn14/rb12 24 an11/sdo1/ocfb/ctpls/cn13/rb13 an11/sdo1/ocfb/ctpls/cn13/rb13 25 cv ref /an10/c3inb/rtcc/c1out/ocfa/cted5/ int1/ cn12/rb14 cv ref /an10/c3inb/rtcc/c1out/ocfa/cted5/ int1/ cn12/ rb14 26 an9/c3ina/t3ck/t2ck/refo/ss1 /cted6/cn11/rb15 an9/c3ina/t3ck/t2ck/refo/ss1 /cted6/cn11/rb15 27 v ss /av ss v ss /av ss 28 v dd /av dd v dd /av dd pic24fxxka302 legend: pin numbers in bold indicate pin function differences between pic24fv and pic24f devices. note 1: alternative multiplexing for sda1(asda1) and scl1 ( ascl1) when the i2csel configuration bit is set. 2: pic24f32ka304 device pins have a maximum voltage of 3.6v and are not 5v tolerant
? 2011 microchip technology inc. ds39995b-page 7 pic24fv32ka304 family pin diagrams legend: pin numbers in bold indicate pin function differences between pic24fv and pic24f devices. note 1: exposed pad on underside of device is connected to v ss . 2: alternative multiplexing for sda1 (asda1) and scl1 (ascl1) when the i2csel configuration bit is set. 3: pic24f32ka304 device pins have a maximum vo ltage of 3.6v and are not 5v tolerant. 28-pin qfn (1,2,3) 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 24fvxxka302 5 4 mclr /ra5 v ss v dd ra0 ra1 v dd v ss rb0 rb6 ra4 rb4 ra7 ra3 ra2 ra6 or v cap rb7 rb9 rb8 rb3 rb2 rb1 rb15 rb14 rb13 rb12 rb10 rb11 rb5 pin pin features pic24fvxxka302 pic24fxxka302 1 pged1/an2/ulpwu/ctcmp/c1ind/c2inb/c3ind/u2tx/cn4/rb0 pged1/an2/ulpwu/ctcmp/c1ind/c2inb/c3ind/u2tx/cn4/rb0 2 pgec1/an3/c1inc/c2ina/u2rx/cted12/cn5/rb1 pgec1/an3/c1inc/c2ina/u2rx/cted12/cn5/rb1 3 an4/c1inb/c2ind/sda2/t5ck/t4ck/u1rx/cted13/cn6/rb2 an4/c1inb/c2ind/sda2/t5ck/t4ck/u1rx/cted13/cn6/rb2 4 an5/c1ina/c2inc/scl2/cn7/rb3 an5/c1ina/c2inc/scl2/cn7/rb3 5v ss v ss 6 osci/an13/clki/cn30/ra2 osci/an13/clki/cn30/ra2 7 osco/an14/clko/cn29/ra3 osco/an14/clko/cn29/ra3 8 sosci/an15/u2rts /cn1/rb4 sosci/an15/u2rts /cn1/rb4 9 sosco/sclki/u2cts /cn0/ra4 sosco/sclki/u2cts /cn0/ra4 10 v dd v dd 11 pged3/asda1 (2) /sck2/cn27/rb5 pged3/asda1 (2) /sck2/cn27/rb5 12 pgec3/ascl1 (2) /sdo2/cn24/rb6 pgec3/ascl1 (2) /sdo2/cn24/rb6 13 u1tx/c2out/oc1/int0/cn23/rb7 u1tx/int0/cn23/rb7 14 scl1/u1cts /c3out/cted10/cn22/rb8 scl1/u1cts /c3out/cted10/cn22/rb8 15 sda1/t1ck/u1rts /ic2/cted4/cn21/rb9 sda1/t1ck/u1rts /ic2/cted4/cn21/rb9 16 sdi2/ic1/cted3/cn9/ra7 sdi2/ic1/cted3/cn9/ra7 17 v cap c2out/oc1/cted1/int2/cn8/ra6 18 pged2/sdi1/oc3/cted11/cn16/rb10 pged2/sdi1/oc3/cted11/cn16/rb10 19 pgec2/sck1/oc2/cted9/cn15/rb11 pgec2/sck1/oc2/cted9/cn15/rb11 20 an12/lvdin/ss2 /ic3/cted2/int2/cn14/rb12 an12/lvdin/ss2 /ic3/cted2/cn14/rb12 21 an11/sdo1/ocfb/ctpls/cn13/rb13 an11/sdo1/ocfb/ctpls/cn13/rb13 22 cv ref /an10/c3inb/rtcc/c1out/ocfa/cted5/ int1/ cn12/ rb14 cv ref /an10/c3inb/rtcc/c1out/ocfa/cted5/ int1/ cn12/ rb14 23 an9/c3ina/t3ck/t2ck/refo/ss1 /cted6/cn11/rb15 an9/c3ina/t3ck/t2ck/refo/ss1 /cted6/cn11/rb15 24 v ss /av ss v ss /av ss 25 v dd /av dd v dd /av dd 26 mclr /v pp /ra5 mclr /v pp /ra5 27 v ref +/cv ref +/an0/c3inc/cted1/cn2/ra0 v ref +/cv ref +/an0/c3inc/cted1/cn2/ra0 28 cv ref -/v ref -/an1/cn3/ra1 cv ref -/v ref -/an1/cn3/ra1 24fxxka302
pic24fv32ka304 family ds39995b-page 8 ? 2011 microchip technology inc. pin diagrams legend: pin numbers in bold indicate pin function differences between pic24fv and pic24f devices. note 1: exposed pad on underside of device is connected to v ss . 2: alternative multiplexing for sda1 (asda1) and scl1 (ascl1) when the i2csel configuration bit is set. 3: pic24f32ka304 device pins have a maximum voltage of 3.6v and are not 5v tolerant. pin pin features pic24fvxxka304 pic24fxxka304 1 sda1/t1ck/u1rts /cted4/cn21/ rb9 sda1/t1ck/u1rts /cted4/cn21/ rb9 2 u1rx/cn18/rc6 u1rx/cn18/rc6 3 u1tx/cn17/rc7 u1tx/cn17/rc7 4 oc2/cn20/rc8 oc2/cn20/rc8 5 ic2/cted7/cn19/rc9 ic2/cted7/cn19/rc9 6 ic1/cted3/cn9/ra7 ic1/cted3/cn9/ra7 7v cap c2out/oc1/cted1/int2/cn8/ra6 8 pged2/sdi1/cted11/cn16/rb10 pged2/sdi1/cted11/cn16/rb10 9 pgec2/sck1/cted9/cn15/rb11 pgec2/sck1/cted9/cn15/rb11 10 an12/lvdin/cted2/int2/cn14/ rb12 an12/lvdin/cted2/cn14/rb12 11 an11/sdo1/ctpls/cn13/rb13 an11/sdo1/ctpls/cn13/rb13 12 oc3/cn35/ra10 oc3/cn35/ra10 13 ic3/cted8/cn36/ra11 ic3/cted8/cn36/ra11 14 cv ref /an10/c3inb/rtcc/ c1out/ocfa/cted5/int1 / cn12/ rb14 cv ref /an10/c3inb/rtcc/ c1out/ocfa/cted5/int1 / cn12/ rb14 15 an9/c3ina/t3ck/t2ck/refo/ ss1 /cted6/cn11/rb15 an9/c3ina/t3ck/t2ck/refo/ ss1 /cted6/cn11/rb15 16 v ss /av ss v ss /av ss 17 v dd /av dd v dd /av dd 18 mclr /v pp /ra5 mclr /v pp /ra5 19 v ref +/cv ref +/an0/c3inc/ cted1/cn2/ra0 v ref +/cv ref +/an0/c3inc/cn2/ ra0 20 cv ref -/v ref -/an1/cn3/ra1 cv ref -/v ref -/an1/cn3/ra1 21 pged1/an2/ulpwu/ctcmp/ c1ind/c2inb/c3ind/u2tx/cn4/rb0 pged1/an2/ulpwu/ctcmp/c1ind/ c2inb/c3ind/u2tx/cn4/rb0 22 pgec1/an3/c1inc/c2ina/u2rx/ cted12/cn5/rb1 pgec1/an3/c1inc/c2ina/u2rx/ cted12/cn5/rb1 23 an4/c1inb/c2ind/sda2/t5ck/ t4ck/cted13/cn6/rb2 an4/c1inb/c2ind/sda2/t5ck/ t4ck/cted13/cn6/rb2 24 an5/c1ina/c2inc/scl2/cn7/ rb3 an5/c1ina/c2inc/scl2/cn7/rb3 25 an6/cn32/rc0 an6/cn32/rc0 26 an7/cn31/rc1 an7/cn31/rc1 27 an8/cn10/rc2 an8/cn10/rc2 28 v dd v dd 29 v ss v ss 30 osci/an13/clki/cn30/ra2 osci/an13/clki/cn30/ra2 31 osco/an14/clko/cn29/ra3 osco/an14/clko/cn29/ra3 32 ocfb/cn33/ra8 ocfb/cn33/ra8 33 sosci/an15/u2rts /cn1/rb4 sosci/an15/u2rts /cn1/rb4 34 sosco/sclki/u2cts /cn0/ra4 sosco/sclki/u2cts /cn0/ra4 35 ss2 /cn34/ra9 ss2 /cn34/ra9 36 sdi2/cn28/rc3 sdi2/cn28/rc3 37 sdo2/cn25/rc4 sdo2/cn25/rc4 38 sck2/cn26/rc5 sck2/cn26/rc5 39 v ss v ss 40 v dd v dd 41 pged3/asda1 (2) /cn27/rb5 pged3/asda1 (2) /cn27/rb5 42 pgec3/ascl1 (2) /cn24/rb6 pgec3/ascl1 (2) /cn24/rb6 43 int0 / cn23/rb7 int0 / cn23/rb7 44 scl1/u1cts /c3out/cted10/ cn22/rb8 scl1/u1cts /c3out/cted10/ cn22/rb8 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic24fvxxka304 37 rb8 rb7 rb6 rb5 v dd v ss rc5 rc4 rc3 ra9 ra4 rb4 ra8 ra3 ra2 v ss v dd rc2 rc1 rc0 rb3 rb2 rb9 rc6 rc7 rc8 rc9 ra7 ra6 or v cap rb10 rb11 rb12 rb13 rb1 rb0 ra1 ra0 mclr /ra5 v dd v ss rb15 rb14 ra11 ra10 44-pin tqfp/qfn (1,2,3) pic24fxxka304
? 2011 microchip technology inc. ds39995b-page 9 pic24fv32ka304 family pin diagrams pin pin features pic24fvxxka304 pic24fxxka304 1 sda1/t1ck/u1rts /cted4/cn21/rb9 sda1/t1ck/u1rts /cted4/cn21/ rb9 2 u1rx/cn18/rc6 u1rx/cn18/rc6 3 u1tx/cn17/rc7 u1tx/cn17/rc7 4 oc2/cn20/rc8 oc2/cn20/rc8 5 ic2/cted7/cn19/rc9 ic2/cted7/cn19/rc9 6 ic1/cted3/cn9/ra7 ic1/cted3/cn9/ra7 7v cap int2/ra6 8n/c n/c 9 pged2/sdi1/cted11/cn16/rb10 pged2/sdi1/cted11/cn16/rb10 10 pgec2/sck1/cted9/cn15/rb11 pgec2/sck1/cted9/cn15/rb11 11 an12/lvdin/cted2/ int2/ cn14/rb12 an12/lvdin/cted2/cn14/rb12 12 an11/sdo1/ctpls/cn13/rb13 an11/sdo1/ctpls/cn13/rb13 13 oc3/cn35/ra10 oc3/cn35/ra10 14 ic3/cted8/cn36/ra11 ic3/cted8/cn36/ra11 15 cv ref /an10/c3inb/rtcc/ c1out/ocfa/cted5/ int1 / cn12/rb14 cv ref /an10/c3inb/rtcc/c1out/ ocfa/cted5/ int1 / cn12/rb14 16 an9/c3ina/t3ck/t2ck/refo/ ss1 /cted6/cn11/rb15 an9/c3ina/t3ck/t2ck/refo/ ss1 /cted6/cn11/rb15 17 v ss /av ss v ss /av ss 18 v dd /av dd v dd /av dd 19 mclr /ra5 mclr /ra5 20 n/c n/c 21 v ref +/cv ref +/an0/c3inc/ cted1/cn2/ra0 v ref +/cv ref +/an0/c3inc/ cted1/cn2/ra0 22 cv ref -/v ref -/an1/cn3/ra1 cv ref -/v ref -/an1/cn3/ra1 23 pged1/an2/ulpwu/ctcmp/c1ind/ c2inb/c3ind/u2tx/cn4/rb0 pged1/an2/ulpwu/ctcmp/c1ind/ c2inb/c3ind/u2tx/cn4/rb0 24 pgec1/an3/c1inc/c2ina/u2rx/ cted12/cn5/rb1 pgec1/an3/c1inc/c2ina/u2rx/ cted12/cn5/rb1 25 an4/c1inb/c2ind/sda2/t5ck/ t4ck/cted13/cn6/rb2 an4/c1inb/c2ind/sda2/t5ck/ t4ck/cted13/cn6/rb2 26 an5/c1ina/c2inc/scl2/cn7/rb3 an5/c1ina/c2inc/scl2/cn7/rb3 27 an6/cn32/rc0 an6/cn32/rc0 28 an7/cn31/rc1 an7/cn31/rc1 29 an8/cn10/rc2 an8/cn10/rc2 30 v dd v dd 31 v ss v ss 32 n/c n/c 33 osci/an13/clki/cn30/ra2 osci/an13/clki/cn30/ra2 34 osco/an14/clko/cn29/ra3 o sco/an14/clko/cn29/ra3 35 ocfb/cn33/ra8 ocfb/cn33/ra8 36 sosci/an15/u2rts /cn1/rb4 sosci/an15/u2rts /cn1/rb4 37 sosco/sclki/u2cts /cn0/ra4 sosco/sclki/u2cts /cn0/ra4 38 ss2 /cn34/ra9 ss2 /cn34/ra9 39 sdi2/cn28/rc3 sdi2/cn28/rc3 40 sdo2/cn25/rc4 sdo2/cn25/rc4 41 sck2/cn26/rc5 sck2/cn26/rc5 42 v ss v ss 43 v dd v dd 44 n/c n/c 45 pged3/asda1 (2) /cn27/rb5 pged3/asda1 (2) /cn27/rb5 46 pgec3/ascl1 (2) /cn24/rb6 pgec3/ascl1 (2) /cn24/rb6 47 c2out/oc1/ int0 / cn23/rb7 c2out/oc1/ int0 / cn23/rb7 48 scl1/u1cts /c3out/cted10/ cn22/rb8 scl1/u1cts /c3out/cted10/ cn22/rb8 r b 8 r b 7 r b 6 r b 5 n / c v d d v s s r c 5 r c 4 r c 3 r a 9 r a 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 rb9 1 36 rb4 rc6 2 35 ra8 rc7 3 34 ra3 rc8 4 33 ra2 rc9 5 32 n/c ra7 6 pic24fvxxka304 31 v ss ra6 7 30 v dd n/c 8 29 rc2 rb10 9 28 rc1 rb11 10 27 rc0 rb12 11 26 rb3 rb13 12 25 rb2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 r a 1 0 r a 1 1 r b 1 4 r b 1 5 v s s / a v s s v d d / a v d d n / c r a 0 r a 1 r b 0 r b 1 legend: pin numbers in bold indicate pin func- tion differences between pic24fv and pic24f devices. note 1: exposed pad on underside of device is connected to v ss . 2: alternative multiplexing for sda1 (asda1) and scl1 (ascl1) when the i2csel configuration bit is set. 3: pic24f32ka3xx device pins have a maximum voltage of 3.6v and are not 5v tolerant. 48-pin uqfn (1,2,3) pic24fxxka304 m c l r / r a 5
pic24fv32ka304 family ds39995b-page 10 ? 2011 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ........................................................... 13 2.0 guidelines for getting started with 16-bit microcontrollers ................................................................. ....................................... 25 3.0 cpu ........................................................................................................................ ................................................................... 31 4.0 memory organization ......................................................................................................... ........................................................ 37 5.0 flash program memory........................................................................................................ ...................................................... 59 6.0 data eeprom memory .......................................................................................................... ................................................... 67 7.0 resets ...................................................................................................................... .................................................................. 73 8.0 interrupt controller ........................................................................................................ ............................................................. 79 9.0 oscillator configuration ...................................... .............................................................. ........................................................ 117 10.0 power-saving features...................................................................................................... ...................................................... 127 11.0 i/o ports .................................................................................................................. ................................................................. 139 12.0 timer1 .................................................................................................................... ................................................................. 143 13.0 timer2/3 and timer4/5 ...................................................................................................... ....................................................... 145 14.0 input capture with dedicated timers ........................................................................................ ............................................... 151 15.0 output compare with dedicated timers ....................................................................................... ........................................... 155 16.0 serial peripheral interface (spi).......................................................................................... ..................................................... 165 17.0 inter-integrated circuit? (i 2 c?)............................................................................................................................ .................. 173 18.0 universal asynchronous receiver transmitter (uart) ......................................................................... .................................. 181 19.0 real-time clock and calendar (rtcc) ....................................................................................... ........................................... 189 20.0 32-bit programmable cyclic redundancy che ck (crc) generator ................................................................ ........................ 203 21.0 high/low-voltage detect (hlvd)............................................................................................. ................................................ 209 22.0 12-bit a/d converter with threshold detect ................................................................................. ........................................... 211 23.0 comparator module.......................................................................................................... ........................................................ 225 24.0 comparator voltage reference............................................................................................... ................................................. 229 25.0 charge time measurement unit (ctmu) ........................................................................................ ........................................ 231 26.0 special features ........................................................................................................... ........................................................... 239 27.0 development support........................................................................................................ ....................................................... 251 28.0 instruction set summary .................................................................................................... ...................................................... 255 29.0 electrical characteristics ................................................................................................. ......................................................... 263 30.0 packaging information...................................................................................................... ........................................................ 289 appendix a: revision history................................................................................................... .......................................................... 311 index .......................................................................................................................... ........................................................................ 313 the microchip web site ......................................................................................................... ............................................................ 317 customer change notification service ........................................................................................... ................................................... 317 customer support ............................................................................................................... ............................................................... 317 reader response ................................................................................................................ .............................................................. 318 product identification system.................................................................................................. ........................................................... 319
? 2011 microchip technology inc. ds39995b-page 11 pic24fv32ka304 family to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
pic24fv32ka304 family ds39995b-page 12 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 13 pic24fv32ka304 family 1.0 device overview this document contains device-specific information for the following devices: ? pic24fv16ka301, pic24f16ka301 ? pic24fv16ka302, pic24f16ka302 ? pic24fv16ka304, pic24f16ka304 ? pic24fv32ka301, pic24f32ka301 ? pic24fv32ka302, pic24f32ka302 ? pic24fv32ka304, pic24f32ka304 the pic24fv32ka304 family introduces a new line of extreme low-power microchip devices. this is a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. this family also offers a new migration option for those high-performance applications, which may be outgrowing their 8-bit platforms, but do not require the numerical processing power of a digital signal processor. 1.1 core features 1.1.1 16-bit architecture central to all pic24f devices is the 16-bit modified harvard architecture, first introduced with microchip?s dspic ? digital signal controllers. the pic24f cpu core offers a wide range of enhancements, such as: ? 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces ? linear addressing of up to 12 mbytes (program space) and 64 kbytes (data) ? a 16-element working register array with built-in software stack support ? a 17 x 17 hardware multiplier with support for integer math ? hardware support for 32-bit by 16-bit division ? an instruction set that supports multiple addressing modes and is optimized for high-level languages, such as c ? operational performance up to 16 mips 1.1.2 power-saving technology all of the devices in the pic24fv32ka304 family incorporate a range of features that can significantly reduce power consumption during operation. key features include: ? on-the-fly clock switching: the device clock can be changed under software control to the timer1 source or the internal, low-power rc oscillator during operation, allowing users to incorporate power-saving ideas into their software designs. ? doze mode operation: when timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the cpu clock speed can be selectively reduced, allowing incremental power savings without missing a beat. ? instruction-based power-saving modes: there are three instruction-based power-saving modes: - idle mode: the core is shut down while leaving the peripherals active. - sleep mode: the core and peripherals that require the system clock are shut down, leaving the peripherals that use their own clock, or the clock from other devices, active. - deep sleep mode: the core, peripherals (except rtcc and dswdt), flash and sram are shut down. 1.1.3 oscillator options and features the pic24fv32ka304 family offers five different oscillator options, allowing users a range of choices in developing application hardware. these include: ? two crystal modes using crystals or ceramic resonators. ? two external clock modes offering the option of a divide-by-2 clock output. ? two fast internal oscillators (frcs): one with a nominal 8 mhz output and the other with a nominal 500 khz output. these outputs can also be divided under software control to provide clock speed as low as 31 khz or 2 khz. ? a phase locked loop (pll) frequency multiplier, available to the external oscillator modes and the 8 mhz frc oscillator, which allows clock speeds of up to 32 mhz. ? a separate internal rc oscillator (lprc) with a fixed 31 khz output, which provides a low-power option for timing-insensitive applications.
pic24fv32ka304 family ds39995b-page 14 ? 2011 microchip technology inc. the internal oscillator block also provides a stable reference source for the fail-safe clock monitor (fscm). this option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 easy migration regardless of the memory size, all the devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. the consistent pinout scheme used throughout the entire family also helps in migrating to the next larger device. this is true when moving between devices with the same pin count, or even jumping from 20-pin or 28-pin devices to 44-pin/48-pin devices. the pic24f family is pin compatible with devices in the dspic33 family, and shares some compatibility with the pinout schema for pic18 and dspic30. this extends the ability of applications to grow from the relatively simple, to the powerful and complex. 1.2 other special features ? communications: the pic24fv32ka304 family incorporates a range of serial communication peripherals to handle a range of application requirements. there is an i 2 c? module that supports both the master and slave modes of operation. it also comprises uarts with built-in irda ? encoders/decoders and an spi module. ? real-time clock/calendar: this module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. ? 12-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speed. the 16-deep result buffer can be used either in sleep to reduce power, or in active mode to improve throughput. ? charge time measurement unit (ctmu) interface: the pic24fv32ka304 family includes the new ctmu interface module, which can be used for capacitive touch sensing, proximity sensing, and also for precision time measurement and pulse generation. 1.3 details on individual family members devices in the pic24fv32ka304 family are available in 20-pin, 28-pin, 44-pin and 48-pin packages. the general block diagram for all devices is shown in figure 1-1 . the devices are different from each other in four ways: 1. flash program memory (16 kbytes for pic24fv16ka devices, 32 kbytes for pic24fv32ka devices). 2. available i/o pins and ports (18 pins on two ports for 20-pin devices, 22 pins on two ports for 28-pin devices and 38 pins on three ports for 44/48-pin devices). 3. alternate scl and sda pins are available only in 28-pin, 44-pin and 48-pin devices and not in 20-pin devices. 4. members of the pic24fv32ka301 family are available as both standard and high-voltage devices. high-voltage devices designated with an ?fv? in the part number (such as pic24fv32ka304), accommodate an operating v dd range of 2.0v to 5.5v, and have an on-board voltage regulator that powers the core. peripherals operate at v dd . standard devices, designated by ?f? (such as pic24f32ka304), function over a lower v dd range of 1.8v to 3.6v. these parts do not have an internal regulator, and both the core and peripherals operate directly from v dd . all other features for devices in this family are identical; these are summarized in ta b l e 1 - 1 . a list of the pin features available on the pic24fv32ka304 family devices, sorted by function, is provided in table . note: table 1-1 provides the pin location of individual peripheral features and not how they are multiplexed on the same pin. this information is provided in the pinout diagrams on pages 5 , 5 , 6 , 7 , 8 and 9 of the data sheet. multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.
? 2011 microchip technology inc. ds39995b-page 15 pic24fv32ka304 family table 1-1: device features for the pic24fv32ka304 family features pic24fv16ka301 pic24fv32ka301 pic24fv16ka302 pic24fv32ka302 pic24fv16ka304 pic24fv32ka304 operating frequency dc ? 32 mhz program memory (bytes) 16k 32k 16k 32k 16k 32k program memory (instructions) 5632 11264 5632 11264 5632 11264 data memory (bytes) 2048 data eeprom memory (bytes) 512 interrupt sources (soft vectors/ nmi traps) 30 (26/4) i/o ports porta<5:0> portb<15:12,9:7,4,2:0> porta<7,5:0> portb<15:0> porta<11:7,5:0> portb<15:0> portc<9:0> total i/o pins 17 23 38 timers: total number (16-bit) 5 32-bit (from paired 16-bit timers) 2 input capture channels 3 output compare/pwm channels 3 input change notification interrupt 16 22 37 serial communications: uart spi (3-wire/4-wire) 2 i 2 c? 2 12-bit analog-to-digital module (input channels) 12 13 16 analog comparators 3 resets (and delays) por, bor, reset instruction, mclr , wdt, illegal opcode, repeat instruction, hardware traps, configuration word mismatch ( p w r t, o s t, p l l l o c k ) instruction set 76 base instructions, multiple addressing mode variations packages 20-pin pdip/ssop/soic 28-pin spdip/ssop/soic/qfn 44-pin qfn/tqfp 48-pin uqfn
pic24fv32ka304 family ds39995b-page 16 ? 2011 microchip technology inc. table 1-2: device features for the pic24f32ka304 family features pic24f16ka301 pic24f32ka301 pic24f16ka302 pic24f32ka302 pic16f16ka304 pic24f32ka304 operating frequency dc ? 32 mhz program memory (bytes) 16k 32k 16k 32k 16k 32k program memory (instructions) 5632 11264 5632 11264 5632 11264 data memory (bytes) 2048 data eeprom memory (bytes) 512 interrupt sources (soft vectors/ nmi traps) 30 (26/4) i/o ports porta<6:0>, portb<15:12, 9:7, 4, 2:0> porta<7:0>, portb<15:0> porta<11:0>, portb<15:0>, portc<9:0> total i/o pins 18 24 39 timers: total number (16-bit) 5 32-bit (from paired 16-bit timers) 2 input capture channels 3 output compare/pwm channels 3 input change notification interrupt 17 23 38 serial communications: uart spi (3-wire/4-wire) 2 i 2 c? 2 12-bit analog-to-digital module (input channels) 12 13 16 analog comparators 3 resets (and delays) por, bor, reset instruction, mclr , wdt, illegal opcode, repeat instruction, hardware traps, configuration word mismatch ( p w r t, o s t, p l l l o c k ) instruction set 76 base instructions, multiple addressing mode variations packages 20-pin pdip/ssop/soic 28-pin spdip/ssop/soic/qfn 44-pin qfn/tqfp 48-pin uqfn
? 2011 microchip technology inc. ds39995b-page 17 pic24fv32ka304 family figure 1-1: pic24fv32ka304 family general block diagram instruction decode and control 16 pch pcl 16 program counter 16-bit alu 23 24 data bus inst register 16 divide support inst latch 16 ea mux read agu write agu 16 16 8 interrupt controller psv and table data access control block stack control logic repeat control logic data latch data ram address latch address latch program memory data latch 16 address bus literal data 23 control signals 16 16 16 x 16 w reg array multiplier 17x17 porta (1) ra<0:7> portb (1) rb<0:15> note 1: all pins or features are not implemented on all device pi nout configurations. see table 1-3 for i/o port pin descriptions. comparators timer4/5 timer2/3 ctmu ic1-3 adc 12-bit pwm/ spi1 i2c1 cn1-22 (1) uart1/2 data eeprom osci/clki osco/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer bor frc/lprc oscillators dswdt timer1 rtcc refo oc1-3 hlvd portc (1) rc<9:0> precision reference band gap voltage v cap regulator
pic24fv32ka304 family ds39995b-page 18 ? 2011 microchip technology inc. table 1-3: pic24fv32ka304 fa mily pinout descriptions function ffv i/o buffer description pin number pin number 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn an0 2 19 2 27 19 21 2 19 2 27 19 21 i ana a/d analog inputs an1 3 20 3 28 20 22 3 20 3 28 20 22 i ana an2 4 1 4 1 21 23 4 1 4 1 21 23 i ana an3 5 2 5 2 22 24 5 2 5 2 22 24 i ana an4 6 3 6 3 23 25 6 3 6 3 23 25 i ana an5 ? ? 7 4 24 26 ? ? 7 4 24 26 i ana an6 ? ? ? ? 25 27 ? ? ? ? 25 27 i ana an7 ? ? ? ? 26 28 ? ? ? ? 26 28 i ana an8 ? ? ? ? 27 29 ? ? ? ? 27 29 i ana an9 18 15 26 23 15 16 18 15 26 23 15 16 i ana an10 17 14 25 22 14 15 17 14 25 22 14 15 i ana an11 16 13 24 21 11 12 16 13 24 21 11 12 i ana an12 15 12 23 20 10 11 15 12 23 20 10 11 i ana an13 7 4 9 6 30 33 7 4 9 6 30 33 i ana an14 8 5 10 7 31 34 8 5 10 7 31 34 i ana an15 9 6 11 8 33 36 9 6 11 8 33 36 i ana ascl1 ? ? 15 12 42 46 ? ? 15 12 42 46 i/o i 2 c? alternate i 2 c 1 clock input/output asda1 ? ? 14 11 41 45 ? ? 14 11 41 45 i/o i 2 c alternate i 2 c 1 data input/output av dd 20 17 28 25 17 18 20 17 28 25 17 18 i ana a/d supply pins av ss 19 16 27 24 16 17 19 16 27 24 16 17 i ana c1ina 8 5 7 4 24 26 8 5 7 4 24 26 i ana comparator 1 input a (+) c1inb 7 4 6 3 23 25 7 4 6 3 23 25 i ana comparator 1 input b (-) c1inc 5 2 5 2 22 24 5 2 5 2 22 24 i ana comparator 1 input c (+) c1ind 4 1 4 1 21 23 4 1 4 1 21 23 i ana comparator 1 input d (-) c1out 17 14 25 22 14 15 17 14 25 22 14 15 o ? comparator 1 output c2ina 5 2 5 2 22 24 5 2 5 2 22 24 i ana comparator 2 input a (+) c2inb 4 1 4 1 21 23 4 1 4 1 21 23 i ana comparator 2 input b (-) c2inc 8 5 7 4 24 26 8 5 7 4 24 26 i ana comparator 2 input c (+) c2ind 7 4 6 3 23 25 7 4 6 3 23 25 i ana comparator 2 input d (-) c2out 14 11 20 17 7 7 11 8 16 13 43 47 o ? comparator 2 output
? 2011 microchip technology inc. ds39995b-page 19 pic24fv32ka304 family c3ina 18 15 26 23 15 16 18 15 26 23 15 16 i ana comparator 3 input a (+) c3inb 17 14 25 22 14 15 17 14 25 22 14 15 i ana comparator 3 input b (-) c3inc 2 19 2 27 19 21 2 19 2 27 19 21 i ana comparator 3 input c (+) c3ind 4 1 4 1 21 23 4 1 4 1 21 23 i ana comparator 3 input d (-) c3out 12 9 17 14 44 48 12 9 17 14 44 48 o ? comparator 3 output clk i 7 4 9 6 30 33 7 4 9 6 30 33 i ana main clock input clko 8 5 10 7 31 34 8 5 10 7 31 34 o ? system clock output cn0 10 7 12 9 34 37 10 7 12 9 34 37 i st interrupt-on-change inputs cn1 9 6 11 8 33 36 9 6 11 8 33 36 i st cn2 2 19 2 27 19 21 2 19 2 27 19 21 i st cn3 3 20 3 28 20 22 3 20 3 28 20 22 i st cn4 4 1 4 1 21 23 4 1 4 1 21 23 i st cn5 5 2 5 2 22 24 5 2 5 2 22 24 i st cn6 6 3 6 3 23 25 6 3 6 3 23 25 i st cn7 ? ? 7 4 24 26 ?- ? 7 4 24 26 i st cn8 14 11 20 17 7 7 ?- ? ?- ?- ? ?- i st cn9 ?- ?- 19 16 6 6 ?- ? 19 16 6 6 i st cn10 ?- ?- ? ? 27 29 ?- ? ?- ?- 27 29 i st cn11 18 15 26 23 15 16 18 15 26 23 15 16 i st cn12 17 14 25 22 14 15 17 14 25 22 14 15 i st cn13 16 13 24 21 11 12 16 13 24 21 11 12 i st cn14 15 12 23 20 10 11 15 12 23 20 10 11 i st cn15 ?- ?- 22 19 9 10 ?- ? 22 19 9 10 i st cn16 ?- ?- 21 18 8 9 ?- ? 21 18 8 9 i st cn17 ?- ?- ? ? 3 3 ?- ? ? ? 3 3 i st table 1-3: pic24fv32ka304 family pinout descriptions (continued) function ffv i/o buffer description pin number pin number 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn
pic24fv32ka304 family ds39995b-page 20 ? 2011 microchip technology inc. cn18 ? ? ? ? 2 2 ? ? ? ? 2 2 i st cn19 ?- ?- ? ? 5 5 ? ? ? ?- 5 5 i st cn20 ?- ?- ? ? 4 4 ? ? ?- ?- 4 4 i st cn21 13 10 18 15 1 1 13 10 18 15 1 1 i st cn22 12 9 17 14 44 48 12 9 17 14 44 48 i st cn23 11 8 16 13 43 47 11 8 16 13 43 47 i st cn24 ?- ?- 15 12 42 46 ?- ? 15 12 42 46 i st cn25 ?- ?- ? ? 37 40 ?- ? ?- ?- 37 40 i st cn26 ?- ?- ? ? 38 41 ?- ? ?- ?- 38 41 i st cn27 ?- ?- 14 11 41 45 ?- ? 14 11 41 45 i st cn28 ?- ?- ? ? 36 39 ?- ? ?- ?- 36 39 i st cn29 8 5 10 7 31 34 8 5 10 7 31 34 i st cn30 7 4 9 6 30 33 7 4 9 6 30 33 i st cn31 ?- ?- ? ? 26 28 ? ? ? ? 26 28 i st cn32 ?- ?- ? ? 25 27 ? ? ? ? 25 27 i st cn33 ?- ?- ? ? 32 35 ? ? ? ? 32 35 i st cn34 ?- ?- ? ? 35 38 ? ? ? ? 35 38 i st cn35 ?- ?- ? ? 12 13 ? ? ? ? 12 13 i st cn36 ?- ?- ? ? 13 14 ? ? ? ? 13 14 i st cv ref 17 14 25 22 14 15 17 14 25 22 14 15 i ana comparator voltage reference output cv ref + 2 19 2 27 19 21 2 19 2 27 19 21 i ana comparator reference positive input voltage cv ref - 3 20 3 28 20 22 3 20 3 28 20 22 i ana comparator reference negative input voltage ctcmp 4 1 4 1 21 23 4 1 4 1 21 23 i ana ctmu comparator input cted1 11 11 20 17 7 7 11 8 2 27 19 21 i st table 1-3: pic24fv32ka304 family pinout descriptions (continued) function ffv i/o buffer description pin number pin number 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn
? 2011 microchip technology inc. ds39995b-page 21 pic24fv32ka304 family cted2 12 9 17 14 44 48 12 9 17 14 44 48 i st ctmu trigger edge inputs cted3 ? ? 21 18 8 9 ? ? 21 18 8 9 i st cted4 5 2 5 2 22 24 5 2 5 2 22 24 i st cted5 6 3 6 3 23 25 6 3 6 3 23 25 i st cted6 15 12 23 20 10 11 15 12 23 20 10 11 i st cted7 ? ? 19 16 6 6 ? ? 19 16 6 6 i st cted8 13 10 18 15 1 1 13 10 18 15 1 1 i st cted9 17 14 25 22 14 15 17 14 25 22 14 15 i st cted10 18 15 26 23 15 16 18 15 26 23 15 16 i st cted11 ? ? ? ? 5 5 ? ? ? ? 5 5 i st cted12 ? ? ? ? 13 14 ? ? ? ? 13 14 i st cted13 ? ? 22 19 9 10 ? ? 22 19 9 10 i st ctpls 16 13 24 21 11 12 16 13 24 21 11 12 o ? ctmu pulse output hlvdin 15 12 23 20 10 11 15 12 23 20 10 11 i st ic1 11 11 19 16 6 6 11 8 19 16 6 6 i st high/low-voltage detect input ic2 13 10 18 15 5 5 13 10 18 15 5 5 i st input capture 1 input ic3 15 12 23 20 13 14 15 12 23 20 13 14 i st input capture 2 input int0 11 8 16 13 43 47 11 8 16 13 43 47 i st input capture 3 input int1 17 14 25 22 14 15 17 14 25 22 14 15 i st interrupt 0 input int2 14 11 20 17 7 7 15 12 23 20 10 11 i st interrupt 1 input mclr 1 18 1 26 18 19 1 18 1 26 18 19 i st interrupt 2 input oc1 11 11 20 17 7 7 11 8 16 13 43 47 o ? output compare/pwm1 output oc2 4 1 22 19 4 4 4 1 22 19 4 4 o ? output compare/pwm2 output oc3 5 2 21,5 18,2 8,12,22 9,13,24 5 2 21,5 18,2 8,12,22 9,13,24 o ? output compare/pwm3 output ocfa 17 14 25 22 14 15 17 14 25 22 14 15 o ? output compare fault a ofcb 16 13 24 21 11,32 12,35 16 13 24 21 11,32 12,35 o ? output compare fault b osci 7 4 9 6 30 33 7 4 9 6 30 33 i ana main oscillator input osco 8 5 10 7 31 34 8 5 10 7 31 34 o ana main oscillator output pgec1 5 2 5 2 22 24 5 2 5 2 22 24 i/o st icsp? clock 1 pced1 4 1 4 1 21 23 4 1 4 1 21 23 i/o st icsp data 1 pgec2 2 19 22,2 19,27 9,19 10,21 2 19 22,2 19,27 9,19 10,21 i/o st icsp clock 2 table 1-3: pic24fv32ka304 family pinout descriptions (continued) function ffv i/o buffer description pin number pin number 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn
pic24fv32ka304 family ds39995b-page 22 ? 2011 microchip technology inc. pged2 3 20 21,3 18,28 8,20 9,22 3 20 21,3 18,28 8,20 9,22 i/o st icsp data 2 pgec3 10 7 12,15 9,12 34,42 37,46 10 7 12,15 9,12 34,42 37,46 i/o st icsp clock 3 pged3 9 6 11,14 8,11 33,41 36,45 9 6 11,14 8,11 33,41 36,45 i/o st icsp data 3 ra0 2 19 2 27 19 21 2 19 2 27 19 21 i/o st porta pins ra1 3 20 3 28 20 22 3 20 3 28 20 22 i/o st ra2 7 4 9 6 30 33 7 4 9 6 30 33 i/o st ra3 8 5 10 7 31 34 8 5 10 7 31 34 i/o st ra4 10 7 12 9 34 37 10 7 12 9 34 37 i/o st ra5 1 18 1 26 18 19 1 18 1 26 18 19 i/o st ra6 14 11 20 17 7 7 ? ? ? ? ? ? i/o st ra7 ? ? 19 16 6 6 ? ? 19 16 6 6 i/o st ra8 ? ? ? ? 32 35 ? ? ? ? 32 35 i/o st ra9 ? ? ? ? 35 38 ? ? ? ? 35 38 i/o st ra10 ? ? ? ? 12 13 ? ? ? ? 12 13 i/o st ra11 ? ? ? ? 13 14 ? ? ? ? 13 14 i/o st rb0 4 1 4 1 21 23 4 1 4 1 21 23 i/o st portb pins rb1 5 2 5 2 22 24 5 2 5 2 22 24 i/o st rb2 6 3 6 3 23 25 6 3 6 3 23 25 i/o st rb3 ? ? 7 4 24 26 ? ? 7 4 24 26 i/o st rb4 9 6 11 8 33 36 9 6 11 8 33 36 i/o st rb5 ? ? 14 11 41 45 ? ? 14 11 41 45 i/o st rb6 ? ? 15 12 42 46 ? ? 15 12 42 46 i/o st rb7 11 8 16 13 43 47 11 8 16 13 43 47 i/o st rb8 12 9 17 14 44 48 12 9 17 14 44 48 i/o st rb9 13 10 18 15 1 1 13 10 18 15 1 1 i/o st rb10 ? ? 21 18 8 9 ? ? 21 18 8 9 i/o st rb11 ? ? 22 19 9 10 ? ? 22 19 9 10 i/o st rb12 15 12 23 20 10 11 15 12 23 20 10 11 i/o st rb13 16 13 24 21 11 12 16 13 24 21 11 12 i/o st rb14 17 14 25 22 14 15 17 14 25 22 14 15 i/o st rb15 18 15 26 23 15 16 18 15 26 23 15 16 i/o st table 1-3: pic24fv32ka304 family pinout descriptions (continued) function ffv i/o buffer description pin number pin number 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn
? 2011 microchip technology inc. ds39995b-page 23 pic24fv32ka304 family rc0 ? ? ? ? 25 27 ? ? ? ? 25 27 i/o st portc pins rc1 ? ? ? ? 26 28 ? ? ? ? 26 28 i/o st rc2 ? ? ? ? 27 29 ? ? ? ? 27 29 i/o st rc3 ? ? ? ? 36 39 ? ? ? ? 36 39 i/o st rc4 ? ? ? ? 37 40 ? ? ? ? 37 40 i/o st rc5 ? ? ? ? 38 41 ? ? ? ? 38 41 i/o st rc6 ? ? ? ? 2 2 ? ? ? ? 2 2 i/o st rc7 ? ? ? ? 3 3 ? ? ? ? 3 3 i/o st rc8 ? ? ? ? 4 4 ? ? ? ? 4 4 i/o st rc9 ? ? ? ? 5 5 ? ? ? ? 5 5 i/o st refo 18 15 26 23 15 16 18 15 26 23 15 16 o ? reference clock output rtcc 17 14 25 22 14 15 17 14 25 22 14 15 o ? real-time clock/calendar output sck1 15 12 22,23 19,20 9,10 10,11 15 12 22,23 19,20 9,10 10,11 i/o st spi1 serial input/output clock sck2 2 19 2,14 27,11 19,38,41 21,41,45 2 19 2,14 27,11 19,38,41 21,41,45 i/o st spi2 serial input/output clock scl1 12 9 17 14 44 48 12 9 17 14 44 48 i/o i 2 c i2c1 clock input/output scl2 18 15 26,7 23,4 15,24 16,26 18 15 26,7 23,4 15,24 16,26 i/o i 2 c i2c2 clock input/output sclki 10 7 12 9 34 37 10 7 12 9 34 37 i st digital secondary clock input sda1 13 10 18 15 1 1 13 10 18 15 1 1 i/o i 2 c i2c1 data input/output sda2 6 3 6 3 23 25 6 3 6 3 23 25 i/o i 2 c i2c2 data input/output sdi1 17 14 21,25 18,22 8,14 9,15 17 14 21,25 18,22 8,14 9,15 i st spi1 serial data input sdi2 4 1 19,4 16,1 6,21,36 6,23,39 4 1 19,4 16,1 6,21,36 6,23,39 i st spi2 serial data input sdo1 16 13 24 21 11 12 16 13 24 21 11 12 o ? spi1 serial data output sdo2 3 20 3,15 28,12 20,37,42 22,40,46 3 20 3,15 28,12 20,37,42 22,40,46 o ? spi2 serial data output sosci 9 6 11 8 33 36 9 6 11 8 33 36 i ana secondary oscillator input sosco 10 7 12 9 34 37 10 7 12 9 34 37 o ana secondary oscillator output ss1 18 15 26 23 15 16 18 15 26 23 15 16 o ? spi1 slave select ss2 15 12 23 20 10,35 11,38 15 12 23 20 10,35 11,38 o ? spi2 slave select t1ck 13 10 18 15 1 1 13 10 18 15 1 1 i st timer1 clock t2ck 18 15 26 23 15 16 18 15 26 23 15 16 i st timer2 clock t3ck 18 15 26 23 15 16 18 15 26 23 15 16 i st timer3 clock t4ck 6 3 6 3 23 25 6 3 6 3 23 25 i st timer4 clock table 1-3: pic24fv32ka304 family pinout descriptions (continued) function ffv i/o buffer description pin number pin number 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn
pic24fv32ka304 family ds39995b-page 24 ? 2011 microchip technology inc. t5ck 6 3 6 3 23 25 6 3 6 3 23 25 i st timer5 clock u1cts 12 9 17 14 44 48 12 9 17 14 44 48 i st uart1 clear to send input u1rts 13 10 18 15 1 1 13 10 18 15 1 1 o ? uart1 request to send output u1rx 6 3 6 3 2,23 2,25 6 3 6 3 2,23 2,25 i st uart1 receive u1tx 11 8 16 13 3,43 3,47 11 8 16 13 3,43 3,47 o ? uart1 transmit u2cts 10 7 12 9 34 37 10 7 12 9 34 37 i st uart2 clear to send input u2rts 9 6 11 8 33 36 9 6 11 8 33 36 o ? uart2 request to send output u2rx 5 2 5 2 22 24 5 2 5 2 22 24 i st uart2 receive u2tx 4 1 4 1 21 23 4 1 4 1 21 23 o ? uart2 transmit ulpwu 4 1 4 1 21 23 4 1 4 1 21 23 i ana ultra low-power wake-up input v cap ? ? ? ? ? ? 14 11 20 17 7 7 p ? core power v dd 20 17 28,13 25,10 17,28,40 18,30,43 20 17 28,13 25,10 17,28,40 18,30,43 p ? v ref + 2 19 2 27 19 21 2 19 2 27 19 21 i ana a/d reference voltage input (+) v ref - 3 20 3 28 20 22 3 20 3 28 20 22 i ana a/d reference voltage input (-) v ss 19 16 27,8 24,5 16,29,39 17,31,42 19 16 27,8 24,5 16,29,39 17,31,42 p ? table 1-3: pic24fv32ka304 family pinout descriptions (continued) function ffv i/o buffer description pin number pin number 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn 20-pin pdip/ssop/ soic 20-pin qfn 28-pin spdip/ ssop/ soic 28-pin qfn 44-pin qfn/tqfp 48-pin uqfn
? 2011 microchip technology inc. ds39995b-page 25 pic24fv32ka304 family 2.0 guidelines for getting started with 16-bit microcontrollers 2.1 basic connection requirements getting started with the pic24fv32ka304 family family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. the following pins must always be connected: ?all v dd and v ss pins (see section 2.2 ?power supply pins? ) ?all av dd and av ss pins, regardless of whether or not the analog device features are used (see section 2.2 ?power supply pins? ) ?mclr pin (see section 2.3 ?master clear (mclr) pin? ) ?v cap pins (see section 2.4 ?voltage regulator pin (v cap )? ) these pins must also be connected if they are being used in the end application: ? pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 ?icsp pins? ) ? osci and osco pins when an external oscillator source is used (see section 2.6 ?external oscillator pins? ) additionally, the following pins may be required: ?v ref +/v ref - pins are used when external voltage reference for analog modules is implemented the minimum mandatory connections are shown in figure 2-1 . figure 2-1: recommended minimum connections note: the av dd and av ss pins must always be connected, regardless of whether any of the analog modules are being used. pic24fxxkxx v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss c1 r1 v dd mclr v cap r2 c7 c2 (2) c3 (2) c4 (2) c5 (2) c6 (2) key (all values are recommendations): c1 through c6: 0.1 ? f, 20v ceramic c7: 10 ? f, 16v tantalum or ceramic r1: 10 k ? r2: 100 ? to 470 ? note 1: see section 2.4 ?voltage regulator pin (v cap )? for explanation of v cap pin connections. 2: the example shown is for a pic24f device with five v dd /v ss and av dd /av ss pairs. other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. 3: some pic24f k parts do not have a regulator. (1) (3)
pic24fv32ka304 family ds39995b-page 26 ? 2011 microchip technology inc. 2.2 power supply pins 2.2.1 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss , is required. consider the following criteria when using decoupling capacitors: ? value and type of capacitor: a 0.1 ? f (100 nf), 10-20v capacitor is recommended. the capacitor should be a low-esr device, with a resonance frequency in the range of 200 mhz and higher. ceramic capacitors are recommended. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). ? handling high-frequency noise: if the board is experiencing high-frequency noise (upward of tens of mhz), add a second ceramic type capaci- tor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 ? f to 0.001 ? f. place this second capacitor next to each primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 ? f in parallel with 0.001 ? f). ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing pcb trace inductance. 2.2.2 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capac- itor for integrated circuits, including microcontrollers, to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 ? f to 47 ? f. 2.3 master clear (mclr ) pin the mclr pin provides two specific device functions: device reset, and device programming and debugging. if programming and debugging are not required in the end application, a direct connection to v dd may be all that is required. the addition of other components, to help increase the application?s resistance to spurious resets from voltage sags, may be beneficial. a typical configuration is shown in figure 2-1 . other circuit designs may be implemented, depending on the application?s requirements. during programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. therefore, specific values of r1 and c1 will need to be adjusted based on the application and pcb requirements. for example, it is recommended that the capacitor, c1, be isolated from the mclr pin during programming and debugging operations by using a jumper ( figure 2-2 ). the jumper is replaced for normal run-time operations. any components associated with the mclr pin should be placed within 0.25 inch (6 mm) of the pin. figure 2-2: example of mclr pin connections note 1: r1 ?? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r2 ?? 470 ? will limit any current flowing into mclr from the external capacitor, c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c1 r2 r1 v dd mclr pic24fxxkxx jp
? 2011 microchip technology inc. ds39995b-page 27 pic24fv32ka304 family 2.4 voltage regulator pin (v cap ) some of the pic24f k devices have an internal voltage regulator. these devices have the voltage regulator output brought out on the v cap pin. on the pic24f k devices with regulators, a low-esr (< 5 ? ) capacitor is required on the v cap pin to stabilize the voltage regulator output. the v cap pin must not be connected to v dd and must use a capacitor of 10 f connected to ground. the type can be ceramic or tantalum. suitable examples of capacitors are shown in table 2-1 . capacitors with equivalent specifications can be used. designers may use figure 2-3 to evaluate esr equivalence of candidate devices. the placement of this capacitor should be close to v cap . it is recommended that the trace length not exceed 0.25 inch (6 mm). refer to section 29.0 ?electrical characteristics? for additional information. refer to section 29.0 ?electrical characteristics? for information on v dd and v ddcore . figure 2-3: frequency vs. esr performance for suggested v cap note: this section applies only to pic24f k devices with an on-chip voltage regulator. 10 1 0.1 0.01 0.001 0.01 0.1 1 10 100 1000 10,000 frequency (mhz) esr ( ? ) note: typical data measurement at 25c, 0v dc bias. table 2-1: suitable capacitor equivalents make part # nominal capacitance base tolerance rated voltage temp. range tdk c3216x7r1c106k 10 f 10% 16v -55 to 125oc tdk c3216x5r1c106k 10 f 10% 16v -55 to 85oc panasonic ecj-3yx1c106k 10 f 10% 16v -55 to 125oc panasonic ecj-4yb1c106k 10 f 10% 16v -55 to 85oc murata grm32dr71c106ka01l 10 f 10% 16v -55 to 125oc murata grm31cr61c106kc31l 10 f 10% 16v -55 to 85oc
pic24fv32ka304 family ds39995b-page 28 ? 2011 microchip technology inc. 2.4.1 considerations for ceramic capacitors in recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. the low-esr, small physical size and other properties make ceramic capacitors very attractive in many types of applications. ceramic capacitors are suitable for use with the inter- nal voltage regulator of this microcontroller. however, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. typical low-cost, 10 ? f ceramic capacitors are available in x5r, x7r and y5v dielectric ratings (other types are also available, but are less common). the initial toler- ance specifications for these types of capacitors are often specified as 10% to 20% (x5r and x7r), or -20%/+80% (y5v). however, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied dc bias voltage and the temperature. the total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. the x5r and x7r capacitors typically exhibit satisfac- tory temperature stability (ex: 15% over a wide temperature range, but consult the manufacturer?s data sheets for exact specifications). however, y5v capaci- tors typically have extreme temperature tolerance specifications of +22%/-82%. due to the extreme temperature tolerance, a 10 ? f nominal rated y5v type capacitor may not deliver enough total capacitance to meet minimum internal voltage regulator stability and transient response requirements. therefore, y5v capacitors are not recommended for use with the internal regulator if the application must operate over a wide temperature range. in addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of dc voltage applied to the capacitor. this effect can be very signifi- cant, but is often overlooked or is not always documented. a typical dc bias voltage vs. capacitance graph for x7r type capacitors is shown in figure 2-4 . figure 2-4: dc bias voltage vs. capacitance characteristics when selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor volt- age. for example, choose a ceramic capacitor rated at 16v for the 3.3v or 2.5v core voltage. suggested capacitors are shown in table 2-1 . 2.5 icsp pins the pgc and pgd pins are used for in-circuit serial programming? (icsp?) and debugging purposes. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recom- mended, with the value in the range of a few tens of ohms, not to exceed 100 ? . pull-up resistors, series diodes and capacitors on the pgc and pgd pins are not recommended as they will interfere with the programmer/debugger communica- tions to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alter- natively, refer to the ac/dc characteristics and timing requirements information in the respective device flash programming specification for information on capacitive loading limits, and pin input voltage high (v ih ) and input low (v il ) requirements. for device emulation, ensure that the ?communication channel select? (i.e., pgcx/pgdx pins), programmed into the device, matches the physical connections for the icsp to the microchip debugger/emulator tool. for more information on available microchip development tools connection requirements, refer to section 27.0 ?development support? . -80 -70 -60 -50 -40 -30 -20 -10 0 10 5 1011121314151617 dc bias voltage (vdc) capacitance change (%) 01234 67 89 16v capacitor 10v capacitor 6.3v capacitor
? 2011 microchip technology inc. ds39995b-page 29 pic24fv32ka304 family 2.6 external oscillator pins many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to for section 9.0 ?oscillator configuration? details). the oscillator circuit should be placed on the same side of the board as the device. place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator cir- cuit to isolate it from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. layout suggestions are shown in figure 2-5 . in-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. with fine-pitch packages, it is not always possible to com- pletely surround the pins and components. a suitable solution is to tie the broken guard sections to a mirrored ground layer. in all cases, the guard trace(s) must be returned to ground. in planning the application?s routing and i/o assign- ments, ensure that adjacent port pins and other signals, in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). for additional information and design guidance on oscillator circuits, please refer to these microchip application notes, available at the corporate web site ( www.microchip.com ): ? an826, ? crystal oscillator basics and crystal selection for rfpic? and picmicro ? devices? ? an849, ?basic picmicro ? oscillator design? ? an943, ?practical picmicro ? oscillator analysis and design? ? an949, ?making your oscillator work? 2.7 unused i/os unused i/o pins should be configured as outputs and driven to a logic low state. alternatively, connect a 1 k ? to 10 k ? resistor to v ss on unused pins and drive the output to logic low. figure 2-5: suggested placement of the oscillator circuit gnd ` ` ` osc1 osc2 t1oso t1os i copper pour primary oscillator crystal timer1 oscillator crystal device pins primary oscillator c1 c2 t1 oscillator: c1 t1 oscillator: c2 (tied to ground) single-sided and in-line layouts: fine-pitch (dual-sided) layouts: gnd osco osci bottom layer copper pour oscillator crystal top layer copper pour c2 c1 device pins (tied to ground) (tied to ground)
pic24fv32ka304 family ds39995b-page 30 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 31 pic24fv32ka304 family 3.0 cpu the pic24f cpu has a 16-bit (data) modified harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m instructions of user program memory space. a single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. all instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move ( mov.d ) instruction and the table instructions. overhead-free program loop constructs are supported using the repeat instructions, which are interruptible at any point. pic24f devices have sixteen, 16-bit working registers in the programmer?s model. each of the working registers can act as a data, address or address offset register. the 16 th working register (w15) operates as a software stack pointer (ssp) for interrupts and calls. the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k word boundary of either program memory or data eeprom memory, defined by the 8-bit program space visibility page address (psvpag) register. the program to data space mapping feature lets any instruction access program space as if it were data space. the instruction set architecture (isa) has been significantly enhanced beyond that of the pic18, but maintains an acceptable level of backward compatibility. all pic18 instructions and addressing modes are supported, either directly, or through simple macros. many of the isa enhancements have been driven by compiler efficiency needs. the core supports inherent (no operand), relative, literal, memory direct and three groups of addressing modes. all modes support register direct and various register indirect modes. each group offers up to seven addressing modes. instructions are associated with predefined addressing modes depending upon their functional requirements. for most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. as a result, three parameter instructions can be supported, allowing trinary operations (i.e., a + b = c) to be executed in a single cycle. a high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. the multiplier supports signed, unsigned and mixed mode, 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. all multiply instructions execute in a single cycle. the 16-bit alu has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. it operates in conjunction with the repeat instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit integer signed and unsigned division. all divide operations require 19 cycles to complete but are interruptible at any cycle boundary. the pic24f has a vectored exception scheme with up to eight sources of non-maskable traps and up to 118 interrupt sources. each interrupt source can be assigned to one of seven priority levels. a block diagram of the cpu is illustrated in figure 3-1 . 3.1 programmer?s model figure 3-2 displays the programmer?s model for the pic24f. all registers in the programmer?s model are memory mapped and can be manipulated directly by instructions. table 3-1 provides a description of each register. all registers associated with the programmer?s model are memory mapped. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the cpu, refer to the ?pic24f family reference manual? , section 2. ?cpu? (ds39703).
pic24fv32ka304 family ds39995b-page 32 ? 2011 microchip technology inc. figure 3-1: pic24f cp u core block diagram table 3-1: cpu core registers register(s) name description w0 through w15 working register array pc 23-bit program counter sr alu status register splim stack pointer limit value register tblpag table memory page address register psvpag program space visibility page address register rcount repeat loop counter register corcon cpu control register instruction decode and control pch pcl 16 program counter 16-bit alu 23 23 24 23 data bus instruction reg 16 16 x 16 w register array divide support rom latch 16 ea mux ragu wagu 16 16 8 interrupt controller psv and table data access control block stack control logic loop control logic data latch data ram address latch control signals to various blocks program memory data latch address bus 16 literal data 16 16 hardware multiplier 16 to peripheral modules address latch data eeprom
? 2011 microchip technology inc. ds39995b-page 33 pic24fv32ka304 family figure 3-2: programmer?s model novz c tblpag 22 0 7 0 0 15 program counter table memory page alu status register (sr) working/address registers w0 (wreg) w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 frame pointer stack pointer psvpag 7 0 program space visibility ra 0 rcount 15 0 repeat loop counter splim stack pointer limit srl registers or bits are shadowed for push.s and pop.s instructions. 0 0 page address register 15 0 cpu control register (corcon) srh w14 w15 dc ipl 210 ?? ? ? ? ? ? ipl3 psv ???????????? ?? pc divider working registers multiplier registers 15 0 value register address register register
pic24fv32ka304 family ds39995b-page 34 ? 2011 microchip technology inc. 3.2 cpu control registers register 3-1: sr: alu status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hsc ? ? ? ? ? ? ?dc bit 15 bit 8 r/w-0, hsc (1) r/w-0, hsc (1) r/w-0, hsc (1) r-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc ipl2 (2) ipl1 (2) ipl0 (2) ra n ov z c bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 dc: alu half carry/borrow bit 1 = a carry-out from the 4 th low-order bit (for byte-sized data) or 8 th low-order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4 th or 8 th low-order bit of the result has occurred bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (1,2) 111 = cpu interrupt priority level is 7 (15); user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: alu overflow bit 1 = overflow occurred for signed (2?s complement) arithmetic in this arithmetic operation 0 = no overflow has occurred bit 1 z: alu zero bit 1 = an operation, which effects the z bit, has set it at some time in the past 0 = the most recent operation, which effects the z bit, has cleared it (i.e., a non-zero result) bit 0 c: alu carry/borrow bit 1 = a carry-out from the most significant bit (msb) of the result occurred 0 = no carry-out from the most significant bit (msb) of the result occurred note 1: the ipl status bits are read-only when nstdis (intcon1<15>) = 1 . 2: the ipl status bits are concatenated with the ipl3 bit (corcon<3>) to form the cpu interrupt priority level (ipl). the value in parentheses indicates the ipl when ipl3 = 1 .
? 2011 microchip technology inc. ds39995b-page 35 pic24fv32ka304 family 3.3 arithmetic logic unit (alu) the pic24f alu is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. unless otherwise mentioned, arithmetic operations are 2?s complement in nature. depending on the operation, the alu may affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. data for the alu operation can come from the w register array, or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be written to the w register array or a data memory location. the pic24f cpu incorporates hardware support for both multiplication and division. this includes a dedicated hardware multiplier and support hardware division for 16-bit divisor. 3.3.1 multiplier the alu contains a high-speed, 17-bit x 17-bit multiplier. it supports unsigned, signed or mixed sign operation in several multiplication modes: ? 16-bit x 16-bit signed ? 16-bit x 16-bit unsigned ? 16-bit signed x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit unsigned ? 16-bit unsigned x 5-bit (literal) unsigned ? 16-bit unsigned x 16-bit signed ? 8-bit unsigned x 8-bit unsigned register 3-2: corcon: cpu control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0, hsc r/w-0 u-0 u-0 ? ? ? ?ipl3 (1) psv ? ? bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 3 ipl3: cpu interrupt priority level status bit (1) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 psv: program space visibility in data space enable bit 1 = program space is visible in data space 0 = program space is not visible in data space bit 1-0 unimplemented: read as ? 0 ? note 1: user interrupts are disabled when ipl3 = 1 .
pic24fv32ka304 family ds39995b-page 36 ? 2011 microchip technology inc. 3.3.2 divider the divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. sixteen-bit signed and unsigned div instructions can specify any w register for both the 16-bit divisor (wn), and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.3.3 multi-bit shift support the pic24f alu supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. all multi-bit shift instructions only support register direct addressing for both the operand source and result destination. a full summary of instructions that use the shift operation is provided in table 3-2 . table 3-2: instructions that use the si ngle and multi-bit shift operation instruction description asr arithmetic shift right source register by one or more bits. sl shift left source register by one or more bits. lsr logical shift right source register by one or more bits.
pic24fv32ka304 family ds39995b-page 37 ? 2011 microchip technology inc. 4.0 memory organization as harvard architecture devices, the pic24f microcontrollers feature separate program and data memory space and bussing. this architecture also allows the direct access of program memory from the data space during code execution. 4.1 program address space the program address memory space of the pic24fv32ka304 family is 4m instructions. the space is addressable by a 24-bit value derived from either the 23-bit program counter (pc) during program execution, or from a table operation or data space remapping, as described in section 4.3 ?interfacing program and data memory spaces? . user access to the program memory space is restricted to the lower half of the address range (000000h to 7fffffh). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. memory maps for the pic24fv32ka304 family of devices are shown in figure 4-1 . figure 4-1: program space memory ma p for pic24fv32ka304 family devices 000000h 0000feh 000002h 000100h f80010h f80012h fefffeh ffffffh 000004h 000200h 0001feh 000104h configuration memory space user memory space note: memory areas are not displayed to scale. reset address device config registers devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fv32ka304 ff0000h f7fffeh f80000h 800000h 7fffffh reserved unimplemented read ? 0 ? reset address devid (2) goto instruction reserved alternate vector table reserved interrupt vector table pic24fv16ka304 device config registers reserved unimplemented read ? 0 ? 002bfeh user flash program memory (11264 instructions) 7ffe00h data eeprom data eeprom flash program memory (5632 instructions) 0057feh
? 2011 microchip technology inc. ds39995b-page 38 pic24fv32ka304 family 4.1.1 program memory organization the program memory space is organized in word-addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address, as shown in figure 4-2 . program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. this arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. 4.1.2 hard memory vectors all pic24f devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h. pic24f devices also have two interrupt vector tables, located from 000004h to 0000ffh and 000104h to 0001ffh. these vector tables allow each of the many device interrupt sources to be handled by separate isrs. a more detailed discussion of the interrupt vector tables is provided in section 8.1 ?interrupt vector (ivt) table? . 4.1.3 data eeprom in the pic24fv32ka304 family, the data eeprom is mapped to the top of the user program memory space, starting at address, 7ffe00, and expanding up to address, 7fffff. the data eeprom is organized as 16-bit wide memory and 256 words deep. this memory is accessed using table read and write operations similar to the user code memory. 4.1.4 device configuration words table 4-1 provides the addresses of the device configuration words for the pic24fv32ka304 family. their location in the memory map is shown in figure 4-1 . for more information on device configuration words, see section 26.0 ?special features? . table 4-1: device configuration words for pic24fv32ka304 family devices figure 4-2: program memory organization configuration words configuration word addresses fbs f80000 fgs f80004 foscsel f80006 fosc f80008 fwdt f8000a fpor f8000c ficd f8000e fds f80010 0 8 16 pc address 000000h 000002h 000004h 000006h 23 00000000 00000000 00000000 00000000 program memory ?phantom? byte (read as ? 0 ?) least significant word most significant word instruction width 000001h 000003h 000005h 000007h msw address (lsw address)
pic24fv32ka304 family ds39995b-page 39 ? 2011 microchip technology inc. 4.2 data address space the pic24f core has a separate, 16-bit wide data memory space, addressable as a single linear range. the data space is accessed using two address generation units (agus), one each for read and write operations. the data space memory map is shown in figure 4-3 . all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this gives a data space address range of 64 kbytes or 32k words. the lower half of the data memory space (that is, when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility (psv) area (see section 4.3.3 ?reading data from program memory using program space visibility? ). pic24fv32ka304 family devices implement a total of 1024 words of data memory. if an ea points to a location outside of this area, an all zero word or byte will be returned. 4.2.1 data space width the data memory space is organized in byte-addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all the data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. figure 4-3: data space memory map for pic24fv32ka304 family devices 0000h 07feh fffeh lsb address lsb msb msb address 0001h 07ffh 0fffh ffffh 8001h 8000h 7fffh 0801h 0800h near 0ffeh sfr sfr space data ram 7fffh program space visibility area note: data memory areas are not shown to scale. 1ffeh 1fff space data space implemented data ram unimplemented read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 40 pic24fv32ka304 family 4.2.2 data memory organization and alignment to maintain backward compatibility with pic ? devices and improve data space memory usage efficiency, the pic24f instruction set supports both word and byte operations. as a consequence of byte accessibility, all effective address (ea) calculations are internally scaled to step through word-aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] will result in a value of ws + 1 for byte operations and ws + 2 for word operations. data byte reads will read the complete word, which contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and the registers are organized as two parallel, byte-wide entities with shared (word) address decode, but separate write lines. data byte writes only write to the corresponding side of the array or register, which matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap will be generated. if the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed, but the write will not occur. in either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the lsb. the msb is not modified. a sign-extend ( se ) instruction is provided to allow the users to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, users can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 4.2.3 near data space the 8-kbyte area between 0000h and 1fffh is referred to as the near data space. locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. the remainder of the data space is addressable indirectly. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing (mda) with a 16-bit address field. for pic24fv32ka304 family devices, the entire implemented data memory lies in near data space (nds). 4.2.4 sfr space the first 2 kbytes of the near data space, from 0000h to 07ffh, are primarily occupied with special function registers (sfrs). these are used by the pic24f core and peripheral modules for controlling the operation of the device. sfrs are distributed among the modules that they control and are generally grouped together by the module. much of the sfr space contains unused addresses; these are read as ? 0 ?. the sfr space, where the sfrs are actually implemented, is provided in ta b l e 4 - 2 . each implemented area indicates a 32-byte region, where at least one address is implemented as an sfr. a complete listing of implemented sfrs, including their addresses, is provided in table 4-3 through ta b l e 4 - 2 5 . table 4-2: implemented regions of sfr data space sfr space address xx00 xx20 xx40 xx60 xx80 xxa0 xxc0 xxe0 000h core icn interrupts ? 100h timers capture ?compare ? ? ? 200h i 2 c? uart spi ? ?i/o 300h adc/cmtu ? ? ? ? 400h ? ? ? ? ? ? ? ? 500h ? ? ? ? ? ? ? ? 600h ? rtc/comp crc ? ? 700h ? ? system/ds/hlvd nvm/pmd ? ? ? ? legend: ? = no implemented sfrs in this block.
pic24fv32ka304 family ds39995b-page 41 ? 2011 microchip technology inc. table 4-3: cpu core registers map file name start addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets wreg0 0000 wreg0 0000 wreg1 0002 wreg1 0000 wreg2 0004 wreg2 0000 wreg3 0006 wreg3 0000 wreg4 0008 wreg4 0000 wreg5 000a wreg5 0000 wreg6 000c wreg6 0000 wreg7 000e wreg7 0000 wreg8 0010 wreg8 0000 wreg9 0012 wreg9 0000 wreg10 0014 wreg10 0000 wreg11 0016 wreg11 0000 wreg12 0018 wreg12 0000 wreg13 001a wreg13 0000 wreg14 001c wreg14 0000 wreg15 001e wreg15 0000 splim 0020 splim xxxx pcl 002e pcl 0000 pch 0030 ? ? ? ? ? ? ? ? ?pch 0000 tblpag 0032 ? ? ? ? ? ? ? ?tblpag 0000 psvpag 0034 ? ? ? ? ? ? ? ?psvpag 0000 rcount 0036 rcount xxxxx sr 0042 ? ? ? ? ? ? ? dc ipl2 ipl1 ipl0 ra n ov z c 0000 corcon 0044 ? ? ? ? ? ? ? ? ? ? ? ? ipl3 psv ? ? 0000 disicnt 0052 ? ? disicnt xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011 microchip technology inc. ds39995b-page 42 pic24fv32ka304 family table 4-4: icn register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnpd1 0056 cn15pde (1) cn14pde cn13pde cn12pde cn11pde cn10pde (1,2) cn9pde (1) cn8pde (3) cn7pde (1) cn6pde cn5pde cn4pde cn3pde cn2pde cn1pde cn0pde 0000 cnpd2 0058 cn31pde (1,2) cn30pde cn29pde cn28pde (1,2) cn27pde (1) cn26pde (1,2) cn25pde (1,2) cn24pde (1) cn23pde cn22pde cn21pde cn20pde (1,2) cn19pde (1,2) cn18pde (1,2) cn17pde (1,2) cn16pde (1) 0000 cnpd3 005a ? ? ? ? ? ? ? ? ? ? ? cn36pde (1,2) cn35pde (1,2) cn34pde (1,2) cn33pde (1,2) cn32pde (1,2) 0000 cnen1 0062 cn15ie (1) cn14ie cn13ie cn12ie cn11ie cn10ie (1,2) cn9ie (1) cn8ie (3) cn7ie (1) cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0064 cn31ie (1,2) cn30ie cn29ie cn28ie (1,2) cn27ie (1) cn26ie (1,2) cn25ie (1,2) cn24ie (1) cn23ie cn22ie cn21ie cn20ie (1,2) cn19ie (1,2) cn18ie (1,2) cn17ie (1,2) cn16ie (1) 0000 cnen3 0066 ? ? ? ? ? ? ? ? ? ? ? cn36ie (1,2) cn35ie (1,2) cn34ie (1,2) cn33ie (1,2) cn32ie (1,2) 0000 cnpu1 006e cn15pue (1) cn14pue cn13pue cn12pue cn11pue cn10pue (1,2) cn9pue (1) cn8pue (3) cn7pue (1) cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 0070 cn31pue (1,2) cn30pue cn29pue cn28pue (1,2) cn27pue (1) cn26pue (1,2) cn25pue (1,2) cn24pue (1) cn23pue cn22pue cn21pue cn20pue (1,2) cn19pue (1,2) cn18pue (1,2) cn17pue (1,2) cn16pue (1) 0000 cnpu3 0072 ? ? ? ? ? ? ? ? ? ? ? cn36pue (1,2) cn35pue (1,2) cn34pue (1,2) cn33pue (1,2) cn32pue (1,2) 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: these bits are not implemented in 20-pin devices. 2: these bits are not implemented in 28-pin devices. 3: these bits are not implemented in ?fv? devices.
pic24fv32ka304 family ds39995b-page 43 ? 2011 microchip technology inc. table 4-5: interrupt controller register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets intcon1 0080 nstdis ? ? ? ? ? ? ? ? ? ? matherr addrerr stkerr oscfail ? 0000 intcon2 0082 altivt disi ? ? ? ? ? ? ? ? ? ? ? int2ep int1ep int0ep 0000 ifs0 0084 nvmif ? ad1if u1txif u1rxif spi1if spf1if t3if t2if oc2if ic2if ? t1if oc1if ic1if int0if 0000 ifs1 0086 u2txif u2rxif int2if t5if t4if ?oc3if ? ? ? ? int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0088 ? ? ? ? ? ? ? ? ? ?ic3if ? ? ? spi2if spf2if 0000 ifs3 008a ?rtcif ? ? ? ? ? ? ? ? ? ? ? mi2c2if si2c2if ? 0000 ifs4 008c ? ?ctmuif ? ? ? ?hlvdif ? ? ? ? crcif u2erif u1erif ? 0000 ifs5 008e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ulpwuif 0000 iec0 0094 nvmie ? ad1ie u1txie u1rxie spi1ie spf1ie t3ie t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie 0000 iec1 0096 u2txie u2rxie int2ie t5ie t4ie ?oc3ie ? ? ? ? int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0098 ? ? ? ? ? ? ? ? ? ?ic3ie ? ? ? spi2ie spf2ie 0000 iec3 009a ?rtcie ? ? ? ? ? ? ? ? ? ? ? mi2c2ie si2c2ie ? 0000 iec4 009c ? ?ctmuie ? ? ? ?hlvdie ? ? ? ? crcie u2erie u1erie ? 0000 iec5 009e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ulpwuie 0000 ipc0 00a4 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 ? ic1ip2 ic1ip1 ic1ip0 ? int0ip2 int0ip1 int0ip0 4444 ipc1 00a6 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? 4444 ipc2 00a8 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 ? spf1ip2 spf1ip1 spf1ip0 ? t3ip2 t3ip1 t3ip0 4444 ipc3 00aa ? nvmip2 nvmip1 nvmip0 ? ? ? ? ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 4044 ipc4 00ac ? cnip2 cnip1 cnip0 ?cmip2cmip1cmip0 ? mi2c1p2 mi2c1p1 mi2c1p0 ? si2c1p2 si2c1p1 si2c1p0 4444 ipc5 00ae ? ? ? ? ? ? ? ? ? ? ? ? ? int1ip2 int1ip1 int1ip0 0004 ipc6 00b0 ? t4ip2 t4ip1 t4ip0 ? ? ? ? ? oc3ip2 oc3ip1 oc3ip0 ? ? ? ? 4040 ipc7 00b2 ? u2txip2 u2txip1 u2txip0 ? u2rxip2 u2rxip1 u2rxip0 ? int2ip2 int2ip1 int2ip0 ? t5ip2 t5ip1 t5ip0 4440 ipc8 00b4 ? ? ? ? ? ? ? ? ? spi2ip2 spi2ip1 spi2ip0 ? spf2ip2 spf2ip1 spf2ip0 0044 ipc9 00b6 ? ? ? ? ? ? ? ? ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? 0040 ipc12 00bc ? ? ? ? ? mi2c2ip2 mi2c2ip1 mi2c2ip0 ? si2c2ip2 si2c2ip1 si2c2ip0 ? ? ? ? 0440 ipc15 00c2 ? ? ? ? ? rtcip2 rtcip1 rtcip0 ? ? ? ? ? ? ? ? 0400 ipc16 00c4 ? crcip2 crcip1 crcip0 ? u2erip2 u2erip1 u2erip0 ? u1erip2 u1erip1 u1erip0 ? ? ? ? 4440 ipc18 00c8 ? ? ? ? ? ? ? ? ? ? ? ? ? hlvdip2 hlvdip1 hlvdip0 0004 ipc19 00ca ? ? ? ? ? ? ? ? ? ctmuip2 ctmuip1 ctmuip0 ? ? ? ? 0040 ipc20 00cc ? ? ? ? ? ? ? ? ? ? ? ? ? ulpwuip2 ulpwuip1 ulpwuip0 0000 inttreg 00e0 cpuirq ?vhold ? ilr3 ilr2 ilr1 ilr0 ? vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011 microchip technology inc. ds39995b-page 44 pic24fv32ka304 family table 4-6: timer register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 tmr1 0000 pr1 0102 pr1 ffff t1con 0104 ton ?tsidl ? ? ? t1ecs1 t1ecs0 ? tgate tckps1 tckps0 ? tsync tcs ? 0000 tmr2 0106 tmr2 0000 tmr3hld 0108 tmr3hld 0000 tmr3 010a tmr3 0000 pr2 010c pr2 0000 pr3 010e pr3 ffff t2con 0110 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t32 ?tcs ? ffff t3con 0112 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 tmr4 0114 tmr4 0000 tmr5hld 0116 tmr5hld 0000 tmr5 0118 tmr5 0000 pr4 011a pr4 ffff pr5 011c pr5 ffff t4con 011e ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 t45 ?tcs ? 0000 t5con 0120 ton ?tsidl ? ? ? ? ? ? tgate tckps1 tckps0 ? ?tcs ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-7: input capture register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1con1 0140 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic1con2 0142 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic1buf 0144 ic1buf 0000 ic1tmr 0146 ic1tmr xxxx ic2con1 0148 ? ? icsidl ic2tsel2 ic2tsel1 ic2tsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic2con2 014a ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic2buf 014c ic2buf 0000 ic2tmr 014e ic2tmr xxxx ic3con1 0150 ? ? icsidl ic3tsel2 ic3tsel1 ic3tsel0 ? ? ? ici1 ici0 icov icbne icm2 icm1 icm0 0000 ic3con2 0152 ? ? ? ? ? ? ? ic32 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000d ic3buf 0154 ic3buf 0000 ic3tmr 0156 ic3tmr xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fv32ka304 family ds39995b-page 45 ? 2011 microchip technology inc. table 4-8: output compare register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1con1 0190 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc1con2 0192 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc1rs 0194 oc1rs 0000 oc1r 0196 oc1r 0000 oc1tmr 0198 oc1tmr xxxx oc2con1 019a ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc2con2 019c fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc2rs 019e oc2rs 0000 oc2r 01a0 oc2r 0000 oc2tmr 01a2 oc2tmr xxxx oc3con1 01a4 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 ocm1 ocm0 0000 oc3con2 01a6 fltmd fltout flttrien ocinv ? dcb1 dcb0 oc32 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 000c oc3rs 01a8 oc3rs 0000 oc3r 01aa oc3r 0000 oc3tmr 01ac oc3tmr xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011 microchip technology inc. ds39995b-page 46 pic24fv32ka304 family table 4-9: i 2 c? register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets i2c1rcv 0200 ? ? ? ? ? ? ? ? i2crcv 0000 i2c1trn 0202 ? ? ? ? ? ? ? ?i2ctrn 00ff i2c1brg 0204 ? ? ? ? ? ? ? ?i2cbrg 0000 i2c1con 0206 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a psr/w rbf tbf 0000 i2c1add 020a ? ? ? ? ? ?i2cadd 0000 i2c1msk 020c ? ? ? ? ? ? amsk9 amsk8 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 0000 i2c2rcv 0210 ? ? ? ? ? ? ? ? i2crcv 0000 i2c2trn 0212 ? ? ? ? ? ? ? ?i2ctrn 00ff i2c2brg 0214 ? ? ? ? ? ? ? ?i2cbrg 0000 i2c2con 0216 i2cen ? i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c2stat 0218 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d/a psr/w rbf tbf 0000 i2c2add 021a ? ? ? ? ? ?i2cadd 0000 i2c2msk 021c ? ? ? ? ? ? amsk9 amsk8 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-10: uart register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u1txreg 0224 ? ? ? ? ? ? ?u1txreg xxxx u1rxreg 0226 ? ? ? ? ? ? ?u1rxreg 0000 u1brg 0228 brg 0000 u2mode 0230 uarten ? usidl iren rtsmd ? uen1 uen0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel 0000 u2sta 0232 utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt urxisel1 urxisel0 adden ridle perr ferr oerr urxda 0110 u2txreg 0234 ? ? ? ? ? ? ?u2txreg xxxx u2rxreg 0236 ? ? ? ? ? ? ?u2rxreg 0000 u2brg 0238 brg 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fv32ka304 family ds39995b-page 47 ? 2011 microchip technology inc. table 4-11: spi register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets spi1stat 0240 spien ? spisidl ? ? spibec2 spibec1 spibec0 srmpt spirov sr1mpt sisel2 sisel1 sisel0 spitbf spirbf 0000 spi1con1 0242 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi1con2 0244 frmen spifsd spifpol ? ? ? ? ? ? ? ? ? ? ? spife spiben 0000 spi1buf 0248 spi1buf 0000 spi2stat 0260 spien ? spisidl ? ? spibec2 spibec1 spibec0 srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf 0000 spi2con1 0262 ? ? ? dissck dissdo mode16 smp cke ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 0000 spi2con2 0264 frmen spifsd spifpol ? ? ? ? ? ? ? ? ? ? ? spife spiben 0000 spi2buf 0268 spi2buf 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-12: porta register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 (2,3) bit 10 (2,3) bit 9 (2,3) bit 8 (2,3) bit 7 (2) bit 6 (4) bit 5 (1) bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 ? ? ? ? trisa11 trisa10 trisa9 trisa8 trisa7 trisa6 ? trisa4 trisa3 trisa2 trisa1 trisa0 00df porta 02c2 ? ? ? ? ra11 ra10 ra9 ra8 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 ? ? ? ? lata11 lata10 lata9 lata8 lata7 lata6 ? lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 ? ? ? ? oda11 oda10 oda9 oda8 oda7 oda6 ? oda4 oda3 oda2 oda1 oda0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available only when mclre = 1 . 2: these bits are not implemented in 20-pin devices. 3: these bits are not implemented in 28-pin devices. 4: these bits are not implemented in fv devices. table 4-13: portb register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 (1) bit 10 (1) bit 9 bit 8 bit 7 bit 6 (1) bit 5 (1) bit 4 bit 3 (1) bit 2 bit 1 bit 0 all resets trisb 02c8 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb 9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff portb 02ca rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx latb 02cc latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx odcb 02ce odb15 odb14 odb13 odb12 odb11 odb10 odb9 odb8 odb7 odb6 odb5 odb4 odb3 odb2 odb1 odb0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: these bits not implemented in 20-pin devices.
? 2011 microchip technology inc. ds39995b-page 48 pic24fv32ka304 family table 4-14: portc register map (1) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 02d0 ? ? ? ? ? ? trisc9 trisc8 trisc7 trisc6 trisc5 t risc4 trisc3 trisc2 trisc1 trisc0 03ff portc 02d2 ? ? ? ? ? ? rc9 rc8 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx latc 02d4 ? ? ? ? ? ? latc9 latc8 latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx odcc 02d6 ? ? ? ? ? ? odc9 odc8 odc7 odc6 odc5 odc4 odc3 odc2 odc1 odc0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: portc is not implemented in 20-pin devices or 28-pin devices. table 4-15: pad config uration register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets padcfg1 02fc ? ? ? ? ? ? ? ? ? ? smbusdel2 smbusdel1 ? ? ? ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fv32ka304 family ds39995b-page 49 ? 2011 microchip technology inc. table 4-16: adc register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc1buf0 xxxx adc1buf1 0302 adc1buf1 xxxx adc1buf2 0304 adc1buf2 xxxx adc1buf3 0306 adc1buf3 xxxx adc1buf4 0308 adc1buf4 xxxx adc1buf5 030a adc1buf5 xxxx adc1buf6 030c adc1buf6 xxxx adc1buf7 030e adc1buf7 xxxx adc1buf8 0310 adc1buf8 xxxx adc1buf9 0312 adc1buf9 xxxx adc1buf10 0314 adc1buf10 xxxx adc1buf11 0316 adc1buf11 xxxx adc1buf12 0318 adc1buf12 xxxx adc1buf13 031a adc1buf13 xxxx adc1buf14 031c adc1buf14 xxxx adc1buf15 031e adc1buf15 xxxx adc1buf16 0320 adc1buf16 xxxx adc1buf17 0322 adc1buf17 xxxx ad1con1 0340 adon ?adsidl ? ? ? form1 form0 ssrc3 ssrc2 ssrc1 ssrc0 ? asam samp done 0000 ad1con2 0342 pvcfg1 pvcfg0 nvcfg0 offcal bufregen cscna ? ? bufs smpi4 smpi3 smpi2 smpi1 smpi0 bufm alts 0000 ad1con3 0344 adrc extsam ? samc4 samc3 samc2 samc1 samc0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 0000 ad1chs 0348 ch0nb2 ch0nb1 ch0nb0 ch0sb4 ch0sb3 ch0sb2 ch0sb1 ch0sb0 ch0na2 ch0na1 ch0na0 ch0sa4 ch0sa3 ch0sa2 ch0sa1 ch0sa0 0000 ad1cssh 034e ? cssl30 cssl29 cssl28 cssl27 cssl26 ? ? ? ? ? ? ? ? cssl17 cssl16 0000 ad1cssl 0350 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 ad1con5 0354 asen lpen ctmureq bgreq vrsreq ? asint1 asint0 ? ? ? ?wm1wm0cm1cm0 0000 ad1chith 0356 ? ? ? ? ? ? ? ? ? ? ? ? ? ? chh17 chh16 0000 ad1chitl 0358 chh15 chh14 chh13 chh12 chh11 chh10 chh9 chh8 chh7 chh6 chh5 chh4 chh3 chh2 chh1 chh0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2011 microchip technology inc. ds39995b-page 50 pic24fv32ka304 family table 4-17: ctmu register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ctmucon1 035a ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig ? ? ? ? ? ? ? ? 0000 ctmucon2 035c edg1edge edg1pol edg1sel3 edg1sel2 edg1sel1 edg1sel0 edg2 edg1 edg2edge edg2pol edg2sel3 edg2sel2 edg2sel1 edg2sel0 ? ? 0000 ctmuicon 035e itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 ? ? ? ? ? ? ? ? 0000 ad1ctmuenh 0360 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ctmen17 ctmen16 0000 ad1ctmuenl 0362 ctmen15 ctmen14 ctmen13 ctmen12 ctmen11 ctmen10 ctmen9 ctmen8 ctmen7 ctmen6 ctmen5 ctmen4 ctmen3 ctmen2 ctmen1 ctmen0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-18: analog select register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ansa 04e0 ? ? ? ? ? ? ? ? ? ? ? ? ansa3 ansa2 ansa1 ansa0 000f ansb 04e2 ansb15 ansb14 ansb13 ansb12 ? ? ? ? ? ? ? ansb4 ansb3 (1) ansb2 ansb1 ansb0 f01f ansc 04e4 ? ? ? ? ? ? ? ? ? ? ? ? ? ansc2 (1,2) ansc1 (1,2) ansc0 (1) 0007 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: these bits are not implemented in 20-pin devices. 2: these bits are not implemented in 28-pin devices. table 4-19: real-time clock and calendar register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets alrmval 0620 alrmval xxxx alcfgrpt 0622 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 0000 rtcval 0624 rtcval xxxx rcfgcal 0626 rtcen ? rtcwren rtcsync halfsec rtcoe rtcptr1 rtcptr0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 0000 rtcpwc 0628 pwcen pwcpol pwccpre pwcspre rtcclk1 rtcclk0 rtcout1 rtcout0 ? ? ? ? ? ? ? ? xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-20: triple comp arator register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmstat 0630 cmidl ? ? ? ? c3evt c2evt c1evt ? ? ? ? ? c3out c2out c1out xxxx cvrcon 0632 ? ? ? ? ? ? ? ? cvren cvroe cvrss cvr4 cvr3 cvr2 cvr1 cvr0 0000 cm1con 0634 con coe cpol clpwr ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 xxxx cm2con 0636 con coe cpol clpwr ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 cm3con 0638 con coe cpol clpwr ? ? cevt cout evpol1 evpol0 ? cref ? ? cch1 cch0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fv32ka304 family ds39995b-page 51 ? 2011 microchip technology inc. table 4-21: crc register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets crccon1 0640 crcen ? csidl vword4 vword3 vword2 vword1 vword0 crcful crcmpt crcisel crcgo lendian ? ? ? 0000 crccon2 0642 ? ? ? dwidth4 dwidth3 dwidth2 dwidth1 dwidth0 ? ? ? plen4 plen3 plen2 plen1 plen0 0000 crcxorl 0644 x15 x14 x13 x12 x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 ? 0000 crcxorh 0646 x31 x30 x29 x28 x27 x26 x25 x24 x23 x22 x21 x20 x19 x18 x17 x16 0000 crcdatl 0648 crcdatl xxxx crcdath 064a crcdath xxxx crcwdatl 064c crcwdatl xxxx crcwdath 064e crcwdath xxxx legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-22: clock control register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr sboren lvren ? dpslp cm pmslp extr swr swdten wdto sleep idle bor por (note 1) osccon 0742 ? cosc2 cosc1 cosc0 ? nosc2 nosc1 nosc0 clklock ?lock ? cf soscdrv soscen oswen (note 2) clkdiv 0744 roi doze2 doze1 doze0 dozen rcdiv2 rcdiv1 rcdiv0 ? ? ? ? ? ? ? ? 3140 osctun 0748 ? ? ? ? ? ? ? ? ? ? tun5 tun4 tun3 tun2 tun1 tun0 0000 refocon 074e roen ? rosslp rosel rodiv3 rodiv2 rodiv1 rodiv0 ? ? ? ? ? ? ? ? 0000 hlvdcon 0756 hlvden ?hlsidl ? ? ? ? ? vdir bgvst irvst ? hlvdl3 hlvdl2 hlvdl1 hlvdl0 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: rcon register reset values are dependent on type of reset. 2: osccon register reset values are dependent on configuration fuses and by type of reset. table 4-23: deep sleep register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets (1) dscon 0758 dsen ? ? ? ? ? ? rtccwdis ? ? ? ? ulpwdis dsbor release 0000 dswake 075a ? ? ? ? ? ? ? dsint0 dsflt ? ? dswdt dsrtcc dsmclr ? dspor 0000 dsgpr0 075c dsgpr0 0000 dsgpr1 075e dsgpr1 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: the deep sleep registers dsgpr0 and dsgpr1 are only reset on a v dd por event.
? 2011 microchip technology inc. ds39995b-page 52 pic24fv32ka304 family table 4-24: nvm register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr pgmonly ? ? ? ? ? erase nvmop5 nvmop4 nvmop3 nvmop2 nvmop1 nvmop0 0000 nvmkey 0766 ? ? ? ? ? ? ? ? nvmkey 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset value shown is for por only. value on other reset states is dependent on the state of memory write or erase operations at the time of reset. table 4-25: ultra low-power wake-up register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ulpwcon 0768 ulpen ?ulpsidl ? ? ? ? ulpsink ? ? ? ? ? ? ? ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. table 4-26: pmd register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t5md t4md t3md t2md t1md ? ? ? i2c1md u2md u1md spi2md spi1md ? ? adc1md 0000 pmd2 0772 ? ? ? ? ? ic3md ic2md ic1md ? ? ? ? ? oc3md oc2md oc1md 0000 pmd3 0774 ? ? ? ? ? cmpmd rtccmd ? crcpmd ? ? ? ? ?i2c2md ? 0000 pmd4 0776 ? ? ? ? ? ? ? ?ulpwumd ? ? eemd refomd ctmumd hlvdmd ? 0000 legend: ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic24fv32ka304 family ds39995b-page 53 ? 2011 microchip technology inc. 4.2.5 software stack in addition to its use as a working register, the w15 register in pic24f devices is also used as a software stack pointer. the pointer always points to the first available free word and grows from lower to higher addresses. it predecrements for stack pops and post-increments for stack pushes, as shown in figure 4-4 . note that for a pc push during any call instruction, the msb of the pc is zero-extended before the push, ensuring that the msb is always clear. the stack pointer limit value (splim) register, associated with the stack pointer, sets an upper address boundary for the stack. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to ? 0 ? as all stack operations must be word-aligned. whenever an ea is generated, using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim register are equal, and a push operation is performed, a stack error trap will not occur. the stack error trap will occur on a subsequent push operation. thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address, 0df6, in ram, initialize the splim with the value, 0df4. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0800h. this prevents the stack from interfering with the special function register (sfr) space. figure 4-4: call stack frame 4.3 interfacing program and data memory spaces the pic24f architecture uses a 24-bit wide program space and 16-bit wide data space. the architecture is also a modified harvard scheme, meaning that data can also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. apart from the normal execution, the pic24f architecture provides two methods by which the program space can be accessed during operation: ? using table instructions to access individual bytes or words anywhere in the program space ? remapping a portion of the program space into the data space, psv table instructions allow an application to read or write small areas of the program memory. this makes the method ideal for accessing data tables that need to be updated from time to time. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. it can only access the least significant word (lsw) of the program word. 4.3.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table memory page address register (tblpag) is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the most significant bit (msb) of tblpag is used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 8-bit program space visibility page address register (psvpag) is used to define a 16k word page in the program space. when the msb of the ea is ? 1 ?, psvpag is concatenated with the lower 15 bits of the ea to form a 23-bit program space address. unlike the table operations, this limits remapping operations strictly to the user memory area. table 4-27 and figure 4-5 show how the program ea is created for table operations and remapping accesses from the data ea. here, p<23:0> bits refer to a program space word, whereas the d<15:0> bits refer to a data space word. note: a pc push during exception processing will concatenate the srl register to the msb of the pc prior to the push. note: a write to the splim register should not be immediately followed by an indirect read operation using w15. pc<15:0> 000000000 0 15 w15 (before call ) w15 (after call ) stack grows towards higher address 0000h pc<22:16> pop : [--w15] push : [w15++]
? 2011 microchip technology inc. ds39995b-page 54 pic24fv32ka304 family table 4-27: program space address construction figure 4-5: data access from program space address generation access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 psvpag<7:0> (2) data ea<14:0> (1) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always ? 1 ? in this case, but is not used in calculating the program space address. bit 15 of the address is psvpag<0>. 2: psvpag can have only two values (? 00 ? to access program memory and ff to access data eeprom) on the pic24fv32ka304 family. 0 program counter 23 bits 1 psvpag 8 bits ea 15 bits program counter (1) select tblpag 8 bits ea 16 bits byte select 0 0 1/0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1/0 0 note 1: the lsb of program space addres ses is always fixed as ? 0 ? in order to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word-aligned. t able read operations are permi tted in the configuration memory space.
pic24fv32ka304 family ds39995b-page 55 ? 2011 microchip technology inc. 4.3.2 data access from program memory and data eeprom memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. it also offers a direct method of reading or writing a word of any address within data eeprom memory. the tblrdh and tblwth instructions are the only method to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit word-wide address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space which contains the least significant data word, and tblrdh and tblwth access the space which contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. 1. tblrdl (table read low): in word mode, it maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is ? 1 ?; the lower byte is selected when it is ? 0 ?. 2. tblrdh (table read high): in word mode, it maps the entire upper word of a program address (p<23:16>) to a data address. note that d<15:8>, the ?phantom? byte, will always be ? 0 ?. in byte mode, it maps the upper or lower byte of the program word to d<7:0> of the data address, as above. note that the data will always be ? 0 ? when the upper ?phantom? byte is selected (byte select = 1 ). note: the tblrdh and tblwth instructions are not used while accessing data eeprom memory.
? 2011 microchip technology inc. ds39995b-page 56 pic24fv32ka304 family in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 5.0 ?flash program memory? . for all table operations, the area of program memory space to be accessed is determined by the table memory page address register (tblpag). tblpag covers the entire program memory space of the device, including user and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-6: accessing program memory with table instructions note: only table read operations will execute in the configuration memory space, and only then, in implemented areas, such as the device id. table write operations are not allowed. 0 8 16 23 00000000 00000000 00000000 00000000 ?phantom? byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 00 000000h 800000h 002bfeh program space data ea<15:0> the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are provided; write op erations are also valid in the user memory area.
? 2011 microchip technology inc. ds39995b-page 57 pic24fv32ka304 family 4.3.3 reading data from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into an 16k word page (in pic24fv16ka3xx devices) and a 32k word page (in pic24fv32ka3xx devices) of the program space. this provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., tblrdl/h ). program space access through the data space occurs if the msb of the data space ea is ? 1 ? and psv is enabled by setting the psv bit in the cpu control (corcon<2>) register. the location of the program memory space to be mapped into the data space is determined by the program space visibility page address (psvpag) register. this 8-bit register defines any one of 256 possible pages of 16k words in program space. in effect, psvpag functions as the upper 8 bits of the program memory address, with the 15 bits of the ea functioning as the lower bits. by incrementing the pc by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. data reads from this area add an additional cycle to the instruction being executed, since two program memory fetches are required. although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see figure 4-7), only the lower 16 bits of the 24-bit program word are used to contain the data. the upper 8 bits of any program space location used as data should be programmed with ? 1111 1111 ? or ? 0000 0000 ? to force a nop . this prevents possible issues should the area of code ever be accidentally executed. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions will require one instruction cycle in addition to the specified execution time. all other instructions will require two instruction cycles in addition to the specified execution time. for operations that use psv, which are executed inside a repeat loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: ? execution in the first iteration ? execution in the last iteration ? execution prior to exiting the loop due to an interrupt ? execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop will allow the instruction accessing data, using psv, to execute in a single cycle. figure 4-7: program spac e visibility operation note: psv access is temporarily disabled during table reads/writes. 23 15 0 psvpag data space program space 0000h 8000h ffffh 00 000000h 800000h 002bfeh when corcon<2> = 1 and ea<15> = 1 : psv area the data in the page designated by psvpag is mapped into the upper half of the data memory space.... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the psv area. this corresponds exactly to the same lower 15 bits of the actual program space address.
pic24fv32ka304 family ds39995b-page 58 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 59 pic24fv32ka304 family 5.0 flash program memory the pic24fv32ka304 of devices contains internal flash program memory for storing and executing appli- cation code. the memory is readable, writable and erasable when operating with v dd over 1.8v. flash memory can be programmed in three ways: ? in-circuit serial programming? (icsp?) ? run-time self programming (rtsp) ? enhanced in-circuit serial programming (enhanced icsp) icsp allows a pic24fv32ka304 device to be serially programmed while in the end application circuit. this is simply done with two lines for the programming clock and programming data (which are named pgecx and pgedx, respectively), and three other lines for power (v dd ), ground (v ss ) and master clear/program mode e ntry v oltage (mclr /v pp ). this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or custom firmware to be programmed. run time self programming (rtsp) is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user may write program memory data in blocks of 32 instructions (96 bytes) at a time, and erase program memory in blocks of 32, 64 and 128 instructions (96,192 and 384 bytes) at a time. the nvmop<1:0> (nvmcon<1:0>) bits decide the erase block size. 5.1 table instructions and flash programming regardless of the method used, flash memory programming is done with the table read and write instructions. these allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using the tblpag<7:0> bits and the effective address (ea) from a w register, specified in the table instruction, as depicted in figure 5-1 . the tblrdl and the tblwtl instructions are used to read or write to bits<15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits<23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on flash pro- gramming, refer to the ?pic24f family reference manual? , section 4. ?program memory? (ds39715). 0 program counter 24 bits program tblpag reg 8 bits working reg ea 16 bits using byte 24-bit ea 0 1/0 select table instruction counter using user/configuration space select
pic24fv32ka304 family ds39995b-page 60 ? 2011 microchip technology inc. 5.2 rtsp operation the pic24f flash program memory array is organized into rows of 32 instructions or 96 bytes. rtsp allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time and to program one row at a time. it is also possible to program single words. the 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks and single row write block (96 bytes) are edge-aligned, from the beginning of program memory. when data is written to program memory using tblwt instructions, the data is not written directly to memory. instead, data written using table writes is stored in holding latches until the programming sequence is executed. any number of tblwt instructions can be executed and a write will be successfully performed. however, 32 tblwt instructions are required to write the full row of memory. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by setting the control bits in the nvmcon register. data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. subsequent writes, however, will wipe out any previous writes. all of the table write operations are single-word writes (two instruction cycles), because only the buffers are written. a programming cycle is required for programming each row. 5.3 enhanced in-circuit serial programming enhanced icsp uses an on-board bootloader, known as the program executive, to manage the programming process. using an spi data frame format, the program executive can erase, program and verify program memory. for more information on enhanced icsp, see the device programming specification. 5.4 control registers there are two sfrs used to read and write the program flash memory: nvmcon and nvmkey. the nvmcon register ( register 5-1 ) controls the blocks that need to be erased, which memory type is to be programmed and when the programming cycle starts. nvmkey is a write-only register that is used for write protection. to start a pr ogramming or erase sequence, the user must consecutively write 55h and aah to the nvmkey register. for more information, refer to section 5.5 ?programming operations? . 5.5 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. during a programming or erase operation, the processor stalls (waits) until the operation is finished. setting the wr bit (nvmcon<15>) starts the operation and the wr bit is automatically cleared when the operation is finished. note: writing to a location multiple times without erasing it is not recommended.
? 2011 microchip technology inc. ds39995b-page 61 pic24fv32ka304 family register 5-1: nvmcon: flash memory control register r/so-0, hc r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 wr wren wrerr pgmonly (4) ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? erase nvmop5 (1) nvmop4 (1) nvmop3 (1) nvmop2 (1) nvmop1 (1) nvmop0 (1) bit 7 bit 0 legend: so = settable only bit hc = hardware clearable bit -n = value at por ?1? = bit is set r = readable bit w = writable bit ?0? = bit is cleared x = bit is unknown u = unimplemented bit, read as ?0? bit 15 wr: write control bit 1 = initiates a flash memory program or erase operation. the operation is self-timed and the bit is cleared by hardware once the operation is complete. 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit 1 = enable flash program/erase operations 0 = inhibit flash program/erase operations bit 13 wrerr: write sequence error flag bit 1 = an improper program or erase s equence attempt or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12 pgmonly: program only enable bit (4) bit 11-7 unimplemented: read as ? 0 ? bit 6 erase: erase/program enable bit 1 = perform the erase operation specified by nvmop<5:0> on the next wr command 0 = perform the program operation specified by nvmop<5:0> on the next wr command bit 5-0 nvmop<5:0>: programming operation command byte bits (1) erase operations (when erase bit is ? 1 ?): 1010xx = erase entire boot block (including code-protected boot block) (2) 1001xx = erase entire memory (including boot block, configuration block, general block) (2) 011010 = erase 4 rows of flash memory (3) 011001 = erase 2 rows of flash memory (3) 011000 = erase 1 row of flash memory (3) 0101xx = erase entire configuration block (except code protection bits) 0100xx = erase entire data eeprom (4) 0011xx = erase entire general memory block programming operations 0001xx = write 1 row of flash memory (when erase bit is ? 0 ?) (3) note 1: all other combinations of nvmop<5:0> are no operation. 2: available in icsp? mode only. refer to device programming specification. 3: the address in the table pointer decides which rows will be erased. 4: this bit is used only while accessing data eeprom.
pic24fv32ka304 family ds39995b-page 62 ? 2011 microchip technology inc. 5.5.1 programming algorithm for flash program memory the user can program one row of flash program memory at a time by erasing the programmable row. the general process is as follows: 1. read a row of program memory (32 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase a row (see example 5-1 ): a) set the nvmop bits (nvmcon<5:0>) to ? 011000 ? to configure for row erase. set the erase (nvmcon<6>) and wren (nvmcon<14>) bits. b) write the starting address of the block to be erased into the tblpag and w registers. c) write 55h to nvmkey. d) write aah to nvmkey. e) set the wr bit (nvmcon<15>). the erase cycle begins and the cpu stalls for the duration of the erase cycle. when the erase is done, the wr bit is cleared automatically. 4. write the first 32 instructions from data ram into the program memory buffers (see example 5-1 ). 5. write the program block to flash memory: a) set the nvmop bits to ? 011000 ? to configure for row programming. clear the erase bit and set the wren bit. b) write 55h to nvmkey. c) write aah to nvmkey. d) set the wr bit. the programming cycle begins and the cpu stalls for the duration of the write cycle. when the write to flash memory is done, the wr bit is cleared automatically. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s, as shown in example 5-5 . example 5-1: erasing a program memo ry row ? assembly language code ; set up nvmcon for row erase operation mov #0x4058, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to row to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ; initialize in-page ea[15:0] pointer tblwtl w0, [w0] ; set base address of erase block disi #5 ; block all interrupts for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted
? 2011 microchip technology inc. ds39995b-page 63 pic24fv32ka304 family example 5-2: erasing a program me mory row ? ?c? language code example 5-3: loading the write bu ffers ? assembly language code // c example using mplab c30 int __attribute__ ((space(auto_psv))) progaddr = &progaddr;// global variable located in pgm memory unsigned int offset; //set up pointer to the first memory location to be written tblpag = __builtin_tblpage(&progaddr); // initialize pm page boundary sfr offset = &progaddr & 0xffff; // initialize lower word of address __builtin_tblwtl(offset, 0x0000); // set base address of erase block // with dummy latch write nvmcon = 0x4058; // initialize nvmcon asm("disi #5"); // block all interrupts for next 5 // instructions __builtin_write_nvm(); // c30 function to perform unlock // sequence and set wr ; set up nvmcon for row programming operations mov #0x4004, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000, w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #0x6000, w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0, w2 ; mov #high_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1, w2 ; mov #high_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2, w2 ; mov #high_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ? ? ? ; 32nd_program_word mov #low_word_31, w2 ; mov #high_byte_31, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0] ; write pm high byte into program latch
pic24fv32ka304 family ds39995b-page 64 ? 2011 microchip technology inc. example 5-4: loading the write buffers ? ?c? language code example 5-5: initiating a programming sequence ? assembly language code example 5-6: initiating a programmi ng sequence ? ?c ? language code // c example using mplab c30 #define num_instruction_per_row 64 int __attribute__ ((space(auto_psv))) progaddr = &progaddr;// global variable located in pgm memory unsigned int offset; unsigned int i; unsigned int progdata[2*num_instruction_per_row]; // buffer of data to write //set up nvmcon for row programming nvmcon = 0x4001; // initialize nvmcon //set up pointer to the first memory location to be written tblpag = __builtin_tblpage(&progaddr); // initialize pm page boundary sfr offset = &progaddr & 0xffff; // initialize lower word of address //perform tblwt instructions to write necessary number of latches for(i=0; i < 2*num_instruction_per_row; i++) { __builtin_tblwtl(offset, progdata[i++]); // write to address low word __builtin_tblwth(offset, progdata[i]); // write to upper byte offset = offset + 2; // increment address } disi #5 ; block all interrupts for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; 2 nops required after setting wr nop ; btsc nvmcon, #15 ; wait for the sequence to be completed bra $-2 ; // c example using mplab c30 asm("disi #5"); // block all interrupts for next 5 instructions __builtin_write_nvm(); // perform unlock sequence and set wr
? 2011 microchip technology inc. ds39995b-page 65 pic24fv32ka304 family example 5-7: programming a single word of flash program memory ; setup a pointer to data program memory mov #tblpage(prog_addr), w0 ; mov w0, tblpag ;initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ;initialize a register with program memory address mov #low_word_n, w2 ; mov #high_byte_n, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; setup nvmcon for programming one word to data program memory mov #0x4003, w0 ; mov w0, nvmcon ; set nvmop bits to 0011 disi #5 ; disable interrupts while the key sequence is written mov #0x55, w0 ; write the key sequence mov w0, nvmkey mov #0xaa, w0 mov w0, nvmkey bset nvmcon, #wr ; start the write cycle
pic24fv32ka304 family ds39995b-page 66 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 67 pic24fv32ka304 family 6.0 data eeprom memory the data eeprom memory is a nonvolatile memory (nvm), separate from the program and volatile data ram. data eeprom memory is based on the same flash technology as program memory, and is optimized for both long retention and a higher number of erase/write cycles. the data eeprom is mapped to the top of the user program memory space, with the top address at program memory address, 7ffe00h to 7fffffh. the size of the data eeprom is 256 words in pic24fv32ka304 devices. the data eeprom is organized as 16-bit wide memory. each word is directly addressable, and is readable and writable during normal operation over the entire v dd range. unlike the flash program memory, normal program execution is not stopped during a data eeprom program or erase operation. the data eeprom programming operations are controlled using the three nvm control registers: ? nvmcon: nonvolatile memory control register ? nvmkey: nonvolatile memory key register ? nvmadr: nonvolatile memory address register 6.1 nvmcon register the nvmcon register ( register 6-1 ) is also the primary control register for data eeprom program/erase operations. the upper byte contains the control bits used to start the program or erase cycle, and the flag bit to indicate if the operation was successfully performed. the lower byte of nvmcom configures the type of nvm operation that will be performed. 6.2 nvmkey register the nvmkey is a write-only register that is used to prevent accidental writes or erasures of data eeprom locations. to start any programming or erase sequence, the following instructions must be executed first, in the exact order provided: 1. write 55h to nvmkey. 2. write aah to nvmkey. after this sequence, a write will be allowed to the nvmcon register for one instruction cycle. in most cases, the user will simply need to set the wr bit in the nvmcon register to start the program or erase cycle. interrupts should be disabled during the unlock sequence. the mplab ? c30 c compiler provides a defined library procedure ( builtin_write_nvm ) to perform the unlock sequence. example 6-1 illustrates how the unlock sequence can be performed with in-line assembly. example 6-1: data eeprom unlock sequence note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on data eeprom, refer to the ?pic24f family reference manual? , section 5. ?data eeprom? (ds39720). //disable interrupts for 5 instructions asm volatile("disi #5"); //issue unlock sequence asm volatile("mov #0x55, w0 \n" "mov w0, nvmkey \n" "mov #0xaa, w1 \n" "mov w1, nvmkey \n"); // perform write/erase operations asm volatile ("bset nvmcon, #wr \n" "nop \n" "nop \n");
pic24fv32ka304 family ds39995b-page 68 ? 2011 microchip technology inc. register 6-1: nvmcon: nonvolat ile memory control register r/s-0, hc r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 wr wren wrerr pgmonly ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? erase nvmop5 nvmop4 nvmop3 nvmop2 nvmop1 nvmop0 bit 7 bit 0 legend: hc = hardware clearable bit u = unimplemented bit, read as ?0? r = readable bit w = writable bit s = settable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 wr: write control bit (program or erase) 1 = initiates a data eeprom erase or write cycle (can be set but not cleared in software) 0 = write cycle is complete (cleared automatically by hardware) bit 14 wren: write enable bit (erase or program) 1 = enable an erase or program operation 0 = no operation allowed (device clears this bit on completion of the write/erase operation) bit 13 wrerr: flash error flag bit 1 = a write operation is prematurely terminated (any mclr or wdt reset during programming operation) 0 = the write operation completed successfully bit 12 pgmonly: program only enable bit 1 = write operation is executed without erasing target address(es) first 0 = automatic erase-before-write. write operations are preceded automatically by an erase of target address(es). bit 11-7 unimplemented: read as ? 0 ? bit 6 erase: erase operation select bit 1 = perform an erase operation when wr is set 0 = perform a write operation when wr is set bit 5-0 nvmop<5:0>: programming operation command byte bits erase operations (when erase bit is ? 1 ?): 011010 = erase 8 words 011001 = erase 4 words 011000 = erase 1 word 0100xx = erase entire data eeprom programming operations (when erase bit is ? 0 ?): 001xx = write 1 word
? 2011 microchip technology inc. ds39995b-page 69 pic24fv32ka304 family 6.3 nvm address register as with flash program memory, the nvm address registers, nvmadru and nvmadr, form the 24-bit effective address (ea) of the selected row or word for data eeprom operations. the nvmadru register is used to hold the upper 8 bits of the ea, while the nvmadr register is used to hold the lower 16 bits of the ea. these registers are not mapped into the special function register (sfr) space; instead, they directly capture the ea<23:0> of the last table write instruction that has been executed and selects the data eeprom row to erase. figure 6-1 depicts the program memory ea that is formed for programming and erase operations. like program memory operations, the least significant bit (lsb) of nvmadr is restricted to even addresses. this is because any given address in the data eeprom space consists of only the lower word of the program memory width; the upper word, including the uppermost ?phantom byte?, are unavailable. this means that the lsb of a data eeprom address will always be ? 0 ?. similarly, the most significant bit (msb) of nvmadru is always ? 0 ?, since all addresses lie in the user program space. figure 6-1: data eeprom addressing with tblpag and nvm address registers 6.4 data eeprom operations the eeprom block is accessed using table read and write operations similar to those used for program memory. the tblwth and tblrdh instructions are not required for data eeprom operations since the memory is only 16 bits wide (data on the lower address is valid only). the following programming operations can be performed on the data eeprom: ? erase one, four or eight words ? bulk erase the entire data eeprom ? write one word ? read one word the library procedures are used in the code examples detailed in the following sections. general descriptions of each process are provided for users who are not using the c30 compiler libraries. 24-bit pm address tblpag nvmadr w register ea 7fh xxxxh 0 0 nvmadru note 1: unexpected results will be obtained if the user attempts to read the eeprom while a programming or erase operation is underway. 2: the c30 c compiler includes library procedures to automatically perform the table read and table write operations, manage the table pointer and write buffers, and unlock and initiate memory write sequences. this eliminates the need to create assembler macros or time critical routines in c for each application.
pic24fv32ka304 family ds39995b-page 70 ? 2011 microchip technology inc. 6.4.1 erase data eeprom the data eeprom can be fully erased, or can be partially erased, at three different sizes: one word, four words or eight words. the bits, nvmop<1:0> (nvmcon<1:0>), decide the number of words to be erased. to erase partially from the data eeprom, the following sequence must be followed: 1. configure nvmcon to erase the required number of words: one, four or eight. 2. load tblpag and wreg with the eeprom address to be erased. 3. clear nvmif status bit and enable the nvm interrupt (optional). 4. write the key sequence to nvmkey. 5. set the wr bit to begin erase cycle. 6. either poll the wr bit or wait for the nvm interrupt (nvmif set). a typical erase sequence is provided in example 6-2 . this example shows how to do a one-word erase. similarly, a four-word erase and an eight-word erase can be done. this example uses c library procedures to manage the table pointer ( builtin_tblpage and builtin_tbloffset ) and the erase page pointer ( builtin_tblwtl ). the memory unlock sequence ( builtin_write_nvm ) also sets the wr bit to initiate the operation and returns control when complete. example 6-2: single-word erase int __attribute__ ((space(eedata))) eedata = 0x1234; // global variable located in eeprom unsigned int offset; // set up nvmcon to erase one word of data eeprom nvmcon = 0x4058; // set up a pointer to the eeprom location to be erased tblpag = __builtin_tblpage(&eedata); // initialize ee data page pointer offset = __builtin_tbloffset(&eedata); // initizlize lower word of address __builtin_tblwtl(offset, 0); // write eeprom data to write latch asm volatile ("disi #5"); // disable interrupts for 5 instructions __builtin_write_nvm(); // issue unlock sequence & start write cycle while(nvmconbits.wr=1); // optional: poll wr bit to wait for // write sequence to complete
? 2011 microchip technology inc. ds39995b-page 71 pic24fv32ka304 family 6.4.1.1 data eeprom bulk erase to erase the entire data eeprom (bulk erase), the address registers do not need to be configured because this operation affects the entire data eeprom. the following sequence helps in performing a bulk erase: 1. configure nvmcon to bulk erase mode. 2. clear nvmif status bit and enable nvm interrupt (optional). 3. write the key sequence to nvmkey. 4. set the wr bit to begin erase cycle. 5. either poll the wr bit or wait for the nvm interrupt (nvmif set). a typical bulk erase sequence is provided in example 6-3 . 6.4.2 single-word write to write a single word in the data eeprom, the following sequence must be followed: 1. erase one data eeprom word (as mentioned in the previous section) if pgmonly bit (nvmcon<12>) is set to ? 1 ?. 2. write the data word into the data eeprom latch. 3. program the data word into the eeprom: - configure the nvmcon register to program one eeprom word (nvmcon<5:0> = 0001xx ). - clear nvmif status bit and enable nvm interrupt (optional). - write the key sequence to nvmkey. - set the wr bit to begin erase cycle. - either poll the wr bit or wait for the nvm interrupt (nvmif set). - to get cleared, wait until nvmif is set. a typical single-word write sequence is provided in example 6-4 . example 6-3: data eeprom bulk erase example 6-4: single-word write to data eeprom // set up nvmcon to bulk erase the data eeprom nvmcon = 0x4050; // disable interrupts for 5 instructions asm volatile ("disi #5"); // issue unlock sequence and start erase cycle __builtin_write_nvm(); int __attribute__ ((space(eedata))) eedata = 0x1234; // global variable located in eeprom int newdata; // new data to write to eeprom unsigned int offset; // set up nvmcon to erase one word of data eeprom nvmcon = 0x4004; // set up a pointer to the eeprom location to be erased tblpag = __builtin_tblpage(&eedata); // initialize ee data page pointer offset = __builtin_tbloffset(&eedata); // initizlize lower word of address __builtin_tblwtl(offset, newdata); // write eeprom data to write latch asm volatile ("disi #5"); // disable interrupts for 5 instructions __builtin_write_nvm(); // issue unlock sequence & start write cycle while(nvmconbits.wr=1); // optional: poll wr bit to wait for // write sequence to complete
pic24fv32ka304 family ds39995b-page 72 ? 2011 microchip technology inc. 6.4.3 reading the data eeprom to read a word from data eeprom, the table read instruction is used. since the eeprom array is only 16 bits wide, only the tblrdl instruction is needed. the read operation is performed by loading tblpag and wreg with the address of the eeprom location followed by a tblrdl instruction. a typical read sequence, using the table pointer management ( builtin_tblpage and builtin_tbloffset ) and table read ( builtin_tblrdl ) procedures from the c30 compiler library, is provided in example 6-5 . program space visibility (psv) can also be used to read locations in the data eeprom. example 6-5: reading the data eeprom using the tblrd command int __attribute__ ((space(eedata))) eedata = 0x1234; // global variable located in eeprom int data; // data read from eeprom unsigned int offset; // set up a pointer to the eeprom location to be erased tblpag = __builtin_tblpage(&eedata); // initialize ee data page pointer offset = __builtin_tbloffset(&eedata); // initizlize lower word of address data = __builtin_tblrdl(offset); // write eeprom data to write latch
? 2011 microchip technology inc. ds39995b-page 73 pic24fv32ka304 family 7.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst . the following is a list of device reset sources: ? por: power-on reset ?mclr : pin reset ?swr: reset instruction ? wdtr: watchdog timer reset ? bor: brown-out reset ? low-power bor/deep sleep bor ? trapr: trap conflict reset ? iopuwr: illegal opcode reset ? uwr: uninitialized w register reset a simplified block diagram of the reset module is shown in figure 7-1 . any active source of reset will make the sysrst signal active. many registers associated with the cpu and peripherals are forced to a known reset state. most registers are unaffected by a reset; their status is unknown on power-on reset (por) and unchanged by all other resets. all types of device reset will set a corresponding status bit in the rcon register to indicate the type of reset (see register 7-1 ). a por will clear all bits except for the bor and por bits (rcon<1:0>) which are set. the user may set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software will not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer (wdt) and device power-saving states. the function of these bits is discussed in other sections of this manual. figure 7-1: reset sy stem block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on resets, refer to the ?pic24f family reference manual? , section 40. ?reset with programmable brown-out reset? (ds39728). note: refer to the specific peripheral or cpu section of this manual for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. mclr v dd v dd rise detect por sleep or idle brown-out reset reset instruction wdt module glitch filter bor trap conflict illegal opcode uninitialized w register sysrst boren<1:0> 00 01 10 11 0 rcon sleep 1 configuration mismatch enable voltage regulator (pic24fv32ka3xx only)
pic24fv32ka304 family ds39995b-page 74 ? 2011 microchip technology inc. register 7-1: rcon: re set control register (1) r/w-0, hs r/w-0, hs r/w-0 r/w-0 u-0 r/c-0, hs r/w-0 r/w-0 trapr iopuwr sboren lvren (3) ? dpslp cm pmslp bit 15 bit 8 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-1, hs r/w-1, hs extr swr swdten (2) wdto sleep idle bor por bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13 sboren: software enable/disable of bor bit 1 = bor is turned on in software 0 = bor is turned off in software bit 12 lvren: low-voltage sleep mode (3) 1 = regulated voltage supply provided solely by the low-voltage regulator (lvreg) during sleep 0 = regulated voltage supply provided by the main voltage regulator (hvreg) during sleep (3) bit 11 unimplemented: read as ? 0 ? bit 10 dpslp: deep sleep mode flag bit 1 = deep sleep has occurred 0 = deep sleep has not occurred bit 9 cm: configuration word mismatch reset flag bit 1 = a configuration word mismatch reset has occurred 0 = a configuration word mismatch reset has not occurred bit 8 pmslp: program memory power during sleep bit 1 = program memory bias voltage remains powered during sleep 0 = program memory bias voltage is powered down during sleep and voltage regulator enters standby mode bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit (2) 1 = wdt is enabled 0 = wdt is disabled note 1: all of the reset status bits may be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. 3: on pic24fv32ka3xx parts only, not used on pic24f32ka3xx.
? 2011 microchip technology inc. ds39995b-page 75 pic24fv32ka304 family table 7-1: reset flag bit operation 7.1 clock source selection at reset if clock switching is enabled, the system clock source at device reset is chosen, as shown in table 7-2 . if clock switching is disabled, the system clock source is always selected according to the oscillator configuration bits. for more information, see section 9.0 ?oscillator configuration? . table 7-2: oscillator selection vs. type of reset (clock switching enabled) bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode bit 2 idle: wake-up from idle flag bit 1 = device has been in idle mode 0 = device has not been in idle mode bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred (the bor is also set after a por) 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-up reset has occurred 0 = a power-up reset has not occurred flag bit setting event clearing event trapr (rcon<15>) trap conflict event por iopuwr (rcon<14>) illegal opcode or uninitialized w register access por cm (rcon<9>) configuration mismatch reset por extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por wdto (rcon<4>) wdt time-out pwrsav instruction, por sleep (rcon<3>) pwrsav #sleep instruction por idle (rcon<2>) pwrsav #idle instruction por bor (rcon<1>) por, bor ? por (rcon<0>) por ? dpslp (rcon<10>) pwrsav #sleep instruction with dscon set por note: all reset flag bits may be set or cleared by the user software. register 7-1: rcon: re set control register (1) (continued) note 1: all of the reset status bits may be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is ? 1 ? (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. 3: on pic24fv32ka3xx parts only, not used on pic24f32ka3xx. reset type clock source determinant por fnosc configuration bits (fnosc<10:8>) bor mclr cosc control bits (osccon<14:12>) wdto swr
pic24fv32ka304 family ds39995b-page 76 ? 2011 microchip technology inc. 7.2 device reset times the reset times for various types of device reset are summarized in ta b l e 7 - 3 . note that the system reset signal, sysrst , is released after the por and pwrt delay times expire. the time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the oscillator start-up timer (ost) and the pll lock time. the ost and pll lock times occur in parallel with the applicable sysrst delay times. the fscm delay determines the time at which the fscm begins to monitor the system clock source after the sysrst signal is released. table 7-3: reset delay times for various device resets reset type clock source sysrst delay system clock delay notes por (6) ec t por + t pwrt ? 1, 2 frc, frcdiv t por + t pwrt t frc 1, 2, 3 lprc t por + t pwrt t lprc 1, 2, 3 ecpll t por + t pwrt t lock 1, 2, 4 frcpll t por + t pwrt t frc + t lock 1, 2, 3, 4 xt, hs, sosc t por + t pwrt t ost 1, 2, 5 xtpll, hspll t por + t pwrt t ost + t lock 1, 2, 4, 5 bor ec t pwrt ? 2 frc, frcdiv t pwrt t frc 2, 3 lprc t pwrt t lprc 2, 3 ecpll t pwrt t lock 2, 4 frcpll t pwrt t frc + t lock 2, 3, 4 xt, hs, sosc t pwrt t ost 2, 5 xtpll, hspll t pwrt t frc + t lock 2, 3, 4 all others any clock ? ? none note 1: t por = power-on reset delay. 2: t pwrt = 64 ms nominal if the power-up timer is enabled; otherwise, it is zero. 3: t frc and t lprc = rc oscillator start-up times. 4: t lock = pll lock time. 5: t ost = oscillator start-up timer (ost). a 10-bit counter waits 1024 oscillator periods before releasing oscillator clock to the system. 6: if two-speed start-up is enabled, regardless of the primary oscillator selected, the device starts with frc, and in such cases, frc start-up time is valid. note: for detailed operating frequency and timing specifications, see section 29.0 ?electrical characteristics? .
? 2011 microchip technology inc. ds39995b-page 77 pic24fv32ka304 family 7.2.1 por and long oscillator start-up times the oscillator start-up circuitry and its associated delay timers are not linked to the device reset delays that occur at power-up. some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. therefore, one or more of the following conditions is possible after sysrst is released: ? the oscillator circuit has not begun to oscillate. ? the oscillator start-up timer (ost) has not expired (if a crystal oscillator is used). ? the pll has not achieved a lock (if pll is used). the device will not begin to execute code until a valid clock source has been released to the system. therefore, the oscillator and pll start-up delays must be considered when the reset delay time must be known. 7.2.2 fail-safe clock monitor (fscm) and device resets if the fscm is enabled, it will begin to monitor the system clock source when sysrst is released. if a valid clock source is not available at this time, the device will automatically switch to the frc oscillator and the user can switch to the desired crystal oscillator in the trap service routine (tsr). 7.3 special function register reset states most of the special function registers (sfrs) associated with the pic24f cpu and peripherals are reset to a particular value at a device reset. the sfrs are grouped by their peripheral or cpu function and their reset values are specified in each section of this manual. the reset value for each sfr does not depend on the type of reset with the exception of four registers. the reset value for the reset control register, rcon, will depend on the type of device reset. the reset value for the oscillator control register, osccon, will depend on the type of reset and the programmed values of the fnosc bits in the flash configuration word (foscsel); see table 7-2 . the rcfgcal and nvmcon registers are only affected by a por. 7.4 deep sleep bor (dsbor) deep sleep bor is a very low-power bor circuitry, used when the device is in deep sleep mode. due to low current consumption, accuracy may vary. the dsbor trip point is around 2.0v. dsbor is enabled by configuring dslpbor (fds<6>) = 1 . dslpbor will re-arm the por to ensure the device will reset if v dd drops below the por threshold. 7.5 brown-out reset (bor) the pic24fv32ka304 family devices implement a bor circuit, which provides the user several configuration and power-saving options. the bor is controlled by the borv<1:0> and boren<1:0> configuration bits (fpor<6:5,1:0>). there are a total of four bor configurations, which are provided in table 7-3 . the bor threshold is set by the borv<1:0> bits. if bor is enabled (any values of boren<1:0>, except ? 00 ?), any drop of v dd below the set threshold point will reset the device. the chip will remain in bor until v dd rises above the threshold. if the power-up timer is enabled, it will be invoked after v dd rises above the threshold; then, it will keep the chip in reset for an additional time delay, t pwrt , if v dd drops below the threshold while the power-up timer is running. the chip goes back into a bor and the power-up timer will be initialized. once v dd rises above the threshold, the power-up timer will execute the additional time delay. bor and the power-up timer (pwrt) are indepen- dently configured. enabling the bor reset does not automatically enable the pwrt. 7.5.1 software enabled bor when boren<1:0> = 01 , the bor can be enabled or disabled by the user in software. this is done with the control bit, sboren (rcon<13>). setting sboren enables the bor to function as previously described. clearing the sboren disables the bor entirely. the sboren bit operates only in this mode; otherwise, it is read as ? 0 ?. placing bor under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change the bor configuration. it also allows the user to tailor the incremental current that the bor consumes. while the bor current is typically very small, it may have some impact in low-power applications. note: even when the bor is under software control, the bor reset voltage level is still set by the borv<1:0> configuration bits. it can not be changed in software.
pic24fv32ka304 family ds39995b-page 78 ? 2011 microchip technology inc. 7.5.2 detecting bor when bor is enabled, the bor bit (rcon<1>) is always reset to ? 1 ? on any bor or por event. this makes it difficult to determine if a bor event has occurred just by reading the state of bor alone. a more reliable method is to simultaneously check the state of both por and bor. this assumes that the por and bor bits are reset to ? 0 ? in the software immediately after any por event. if the bor bit is ? 1 ? while por is ? 0 ?, it can be reliably assumed that a bor event has occurred. 7.5.3 disabling bor in sleep mode when boren<1:0> = 10 , bor remains under hardware control and operates as previously described. however, whenever the device enters sleep mode, bor is automatically disabled. when the device returns to any other operating mode, bor is automatically re-enabled. this mode allows for applications to recover from brown-out situations, while actively executing code when the device requires bor protection the most. at the same time, it saves additional power in sleep mode by eliminating the small incremental bor current. note: even when the device exits from deep sleep mode, both the por and bor are set. note: bor levels differ depending on device type; pic24fv32ka3xx devices are at different levels than those of pic24f32ka3xx devices. see section 29.0 ?electrical characteristics? for bor voltage levels.
? 2011 microchip technology inc. ds39995b-page 79 pic24fv32ka304 family 8.0 interrupt controller the pic24f interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the cpu. it has the following features: ? up to eight processor exceptions and software traps ? seven user-selectable priority levels ? interrupt vector table (ivt) with up to 118 vectors ? unique vector for each interrupt or exception source ? fixed priority within a specified user priority level ? alternate interrupt vector table (aivt) for debug support ? fixed interrupt entry and return latencies 8.1 interrupt vector (ivt) table the ivt is shown in figure 8-1 . the ivt resides in the program memory, starting at location, 000004h. the ivt contains 126 vectors, consisting of eight non-maskable trap vectors, plus, up to 118 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. all other things being equal, lower addresses have a higher natural priority. for example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. pic24fv32ka304 family devices implement non-maskable traps and unique interrupts; these are summarized in ta b l e 8 - 1 and tab l e 8 - 2 . 8.1.1 alternate interrupt vector ta b l e (a i v t ) the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 8-1 . access to the aivt is provided by the altivt control bit (intcon2<15>). if the altivt bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. the alternate vectors are organized in the same manner as the default vectors. the aivt supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. this feature also enables switching between applications for evaluation of different software algorithms at run-time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 8.2 reset sequence a device reset is not a true exception, because the interrupt controller is not involved in the reset process. the pic24f devices clear their registers in response to a reset, which forces the program counter (pc) to zero. the microcontroller then begins program execution at location, 000000h. the user programs a goto instruction at the reset address, which redirects the program execution to the appropriate start-up routine. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the interrupt controller, refer to the ?pic24f family reference manual? , section 8. ?interrupts? (ds39707). note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction.
pic24fv32ka304 family ds39995b-page 80 ? 2011 microchip technology inc. figure 8-1: pic24f interrupt vector table reset ? goto instruction 000000h reset ? goto address 000002h reserved 000004h oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 000014h interrupt vector 1 ? ? ? interrupt vector 52 00007ch interrupt vector 53 00007eh interrupt vector 54 000080h ? ? ? interrupt vector 116 0000fch interrupt vector 117 0000feh reserved 000100h reserved 000102h reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector reserved reserved reserved interrupt vector 0 000114h interrupt vector 1 ? ? ? interrupt vector 52 00017ch interrupt vector 53 00017eh interrupt vector 54 000180h ? ? ? interrupt vector 116 interrupt vector 117 0001feh start of code 000200h decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) note 1: see table 8-2 for the interrupt vector list.
? 2011 microchip technology inc. ds39995b-page 81 pic24fv32ka304 family table 8-2: implemented interrupt vectors table 8-1: trap vector details vector number ivt address aivt address trap source 0 000004h 000104h reserved 1 000006h 000106h oscillator failure 2 000008h 000108h address error 3 00000ah 00010ah stack error 4 00000ch 00010ch math error 5 00000eh 00010eh reserved 6 000010h 000110h reserved 7 000012h 000112h reserved interrupt source vector number ivt address aivt address interrupt bit locations flag enable priority adc1 conversion done 13 00002eh 00012eh ifs0<13> iec0<13> ipc3<6:4> comparator event 18 000038h 000138h ifs1<2> iec1<2> ipc4<10:8> crc generator 67 00009ah 00019ah ifs4<3> iec4<3> ipc16<14:12> ctmu 77 0000aeh 0001aeh ifs4<13> iec4<13> ipc19<6:4> external interrupt 0 0 000014h 000114h ifs0<0> iec0<0> ipc0<2:0> external interrupt 1 20 00003ch 00013ch ifs1<4> iec1<4> ipc5<2:0> external interrupt 2 29 00004eh 00014eh ifs1<13> iec1<13> ipc7<6:4> i2c1 master event 17 000036h 000136h ifs1<1> iec1<1> ipc4<6:4> i2c1 slave event 16 000034h 000134h ifs1<0> iec1<0> ipc4<2:0> i2c2 master event 50 000078h 000178h ifs3<2> iec3<2> ipc12<10:8> i2c2 slave event 49 000076h 000176h ifs3<1> iec3<1> ipc12<6:4> input capture 1 1 000016h 000116h ifs0<1> iec0<1> ipc0<6:4> input capture 2 5 00001eh 00011eh ifs0<5> iec0<5> ipc1<6:4> input capture 3 37 00005eh 00015eh ifs2<5> iec2<5> ipc9<6:4> input change notification 19 00003ah 00013ah ifs1<3> iec1<3> ipc4<14:12> hlvd (high/low-voltage detect) 72 0000a4h 0001a4h ifs4<8> iec4<8> ipc17<2:0> nvm ? nvm write complete 15 000032h 000132h ifs0<15> iec0<15> ipc3<14:12> output compare 1 2 000018h 000118h ifs0<2> iec0<2> ipc0<10:8> output compare 2 6 000020h 000120h ifs0<6> iec0<6> ipc1<10:8> output compare 3 25 000046h 000146h ifs1<9> iec1<9> ipc6<6:4> real-time clock/calendar 62 000090h 000190h ifs3<14> iec3<14> ipc15<10:8> spi1 error 9 000026h 000126h ifs0<9> iec0<9> ipc2<6:4> spi1 event 10 000028h 000128h ifs0<10> iec0<10> ipc2<10:8> spi2 error 32 000054h 000154h ifs2<0> iec2<2> ipc8<2:0> spi2 event 33 000056h 000156h ifs2<1> iec2<1> ipc8<6:4> timer1 3 00001ah 00011ah ifs0<3> iec0<3> ipc0<14:12> timer2 7 000022h 000122h ifs0<7> iec0<7> ipc1<14:12> timer3 8 000024h 000124h ifs0<8> iec0<8> ipc2<2:0> timer4 27 00004ah 00014ah ifs1<11> iec1<11> ipc6<14:12> timer5 28 00004ch 00015ch ifs1<12> iec1<12> ipc7<2:0> uart1 error 65 000096h 000196h ifs4<1> iec4<1> ipc16<6:4> uart1 receiver 11 00002ah 00012ah ifs0<11> iec0<11> ipc2<14:12> uart1 transmitter 12 00002ch 00012ch ifs0<12> iec0<12> ipc3<2:0> uart2 error 66 000098h 000198h ifs4<2> iec4<2> ipc16<10:8> uart2 receiver 30 000050h 000150h ifs1<14> iec1<14> ipc7<10:8> uart2 transmitter 31 000052h 000152h ifs1<15> iec1<15> ipc7<14:12> ultra low-power wake-up 80 0000b4h 0001b4h ifs5<0> iec5<0> ipc20<2:0>
pic24fv32ka304 family ds39995b-page 82 ? 2011 microchip technology inc. 8.3 interrupt control and status registers the pic24fv32ka304 family of devices implements a total of 22 registers for the interrupt controller: ? intcon1 ? intcon2 ? ifs0, ifs1, ifs3 and ifs4 ? iec0, iec1, iec3 and iec4 ? ipc0 through ipc5, ipc7 and ipc15 through ipc19 ?inttreg global interrupt control functions are controlled from intcon1 and intcon2. intcon1 contains the interrupt nesting disable (nstdis) bit, as well as the control and status flags for the processor trap sources. the intcon2 register controls the external interrupt request signal behavior and the use of the aiv table. the ifsx registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals, or external signal, and is cleared via software. the iecx registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. the ipcx registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into the vector number (vecnum<6:0>) and the interrupt level (ilr<3:0>) bit fields in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the same sequence listed in table 8-2 . for example, the int0 (external interrupt 0) is depicted as having a vector number and a natural order priority of 0. the int0if status bit is found in ifs0<0>, the int0ie enable bit in iec0<0> and the int0ip<2:0> priority bits are in the first position of ipc0 (ipc0<2:0>). although they are not specifically part of the interrupt control hardware, two of the cpu control registers contain bits that control interrupt functionality. the alu status register (sr) contains the ipl<2:0> bits (sr<7:5>). these indicate the current cpu interrupt priority level. the user may change the current cpu priority level by writing to the ipl bits. the corcon register contains the ipl3 bit, which together with ipl<2:0>, also indicates the current cpu priority level. ipl3 is a read-only bit so that the trap events cannot be masked by the user?s software. all interrupt registers are described in register 8-1 through register 8-33 , in the following sections.
? 2011 microchip technology inc. ds39995b-page 83 pic24fv32ka304 family register 8-1: sr: alu status register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0, hsc ? ? ? ? ? ? ? dc (1) bit 15 bit 8 r/w-0, hsc r/w-0, hsc r/w-0, hsc r-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc r/w-0, hsc ipl2 (2,3) ipl1 (2,3) ipl0 (2,3) ra (1) n (1) ov (1) z (1) c (1) bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2,3) 111 = cpu interrupt priority level is 7 (15); user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: see register 3-1 for the description of these bits, which are not dedicated to interrupt control functions. 2: the ipl bits are concatenated with the ipl3 bit (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the interrupt priority level if ipl3 = 1 . 3: the ipl status bits are read-only when nstdis (intcon1<15>) = 1 . note: bit 8 and bits 4 through 0 are described in section 3.0 ?cpu? .
pic24fv32ka304 family ds39995b-page 84 ? 2011 microchip technology inc. register 8-2: corcon: cpu control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/c-0, hsc r/w-0 u-0 u-0 ? ? ? ?ipl3 (2) psv (1) ? ? bit 7 bit 0 legend: c = clearable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 3 ipl3: cpu interrupt priority level status bit (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 1-0 unimplemented: read as ? 0 ? note 1: see register 3-2 for the description of this bit, which is not dedicated to interrupt control functions. 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. note: bit 2 is described in section 3.0 ?cpu? .
? 2011 microchip technology inc. ds39995b-page 85 pic24fv32ka304 family register 8-3: intcon1: in terrupt control register 1 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 nstdis ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs u-0 ? ? ? matherr addrerr stkerr oscfail ? bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14-5 unimplemented: read as ? 0 ? bit 4 matherr: arithmetic error trap status bit 1 = overflow trap has occurred 0 = overflow trap has not occurred bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 86 ? 2011 microchip technology inc. register 8-4: intcon2: in terrupt control register2 r/w-0 r-0, hsc u-0 u-0 u-0 u-0 u-0 u-0 altivt disi ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? int2ep int1ep int0ep bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = use alternate interrupt vector table 0 = use standard (default) vector table bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-3 unimplemented: read as ? 0 ? bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge
? 2011 microchip technology inc. ds39995b-page 87 pic24fv32ka304 family register 8-5: ifs0: interrupt flag status register 0 r/w-0, hs u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs nvmif ? ad1if u1txif u1rxif spi1if spf1if t3if bit 15 bit 8 r/w-0, hs r/w-0, hs r/w-0, hs u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs t2if oc2if ic2if ? t1if oc1if ic1if int0if bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nvmif: nvm interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 unimplemented: read as ? 0 ? bit 13 ad1if: a/d conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spf1if: spi1 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as ? 0 ? bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
pic24fv32ka304 family ds39995b-page 88 ? 2011 microchip technology inc. bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 8-5: ifs0: interrupt fla g status register 0 (continued) register 8-6: ifs1: interrupt flag status register 1 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs r/w-0, hs u-0 r/w-0, hs u-0 u2txif u2rxif int2if t5if t4if ?oc3if ? bit 15 bit 8 u-0 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-0 r/w-0 ? ? ? int1if cnif cmif mi2c1if si2c1if bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 u2txif: uart2 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 u2rxif: uart2 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 t5if: timer5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 t4if: timer4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 unimplemented: read as ? 0 ? bit 9 oc3if: output compare channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8-5 unimplemented: read as ? 0 ? bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 cmif: comparator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
? 2011 microchip technology inc. ds39995b-page 89 pic24fv32ka304 family bit 1 mi2c1if: master i2c1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: slave i2c1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 8-6: ifs1: interrupt fla g status register 1 (continued) register 8-7: ifs2: interrupt flag status register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0, hs u-0 u-0 u-0 r/w-0, hs r/w-0, hs ? ? ic3if ? ? ? spi2if spf2if bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 ic3if: input capture channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4-2 unimplemented: read as ? 0 ? bit 1 spi2if: spi2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 spf2if: spi2 fault interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
pic24fv32ka304 family ds39995b-page 90 ? 2011 microchip technology inc. register 8-8: ifs3: interrupt flag status register 3 u-0 r/w-0, hs u-0 u-0 u-0 u-0 u-0 u-0 ?rtcif ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0, hs u-0 ? ? ? ? ?mi2c2ifsi2c2if ? bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 rtcif: real-time clock and calendar interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13-3 unimplemented: read as ? 0 ? bit 2 mi2c2if: master i2c2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 si2c2if: slave i2c2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 91 pic24fv32ka304 family register 8-9: ifs4: interrupt flag status register 4 u-0 u-0 r/w-0, hs u-0 u-0 u-0 u-0 r/w-0, hs ? ?ctmuif ? ? ? ?hlvdif bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs u-0 ? ? ? ? crcif u2erif u1erif ? bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ctmuif: ctmu interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-9 unimplemented: read as ? 0 ? bit 8 hlvdif: high/low-voltage detect interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7-4 unimplemented: read as ? 0 ? bit 3 crcif: crc generator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 u2erif: uart2 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 u1erif: uart1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 92 ? 2011 microchip technology inc. register 8-10: ifs5: interrupt flag status register 5 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hs ? ? ? ? ? ? ?ulpwuif bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 unimplemented: read as ? 0 ? bit 0 ulpwuif: ultra low-power wake-up interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred
? 2011 microchip technology inc. ds39995b-page 93 pic24fv32ka304 family register 8-11: iec0: interrupt enable control register 0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmie ? ad1ie u1txie u1rxie spi1ie spf1ie t3ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ie oc2ie ic2ie ? t1ie oc1ie ic1ie int0ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 nvmie: nvm interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 14 unimplemented: read as ? 0 ? bit 13 ad1ie: a/d conversion complete interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 10 spi1ie: spi1 transfer complete interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 9 spf1ie: spi1 fault interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 4 unimplemented: read as ? 0 ? bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled
pic24fv32ka304 family ds39995b-page 94 ? 2011 microchip technology inc. bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 int0ie: external interrupt 0 enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled register 8-11: iec0: interrupt enable control register 0 register 8-12: iec1: interrupt enable control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 u2txie u2rxie int2ie t5ie t4ie ?oc3ie ? bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int1ie cnie cmie mi2c1ie si2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 u2txie: uart2 transmitter interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 14 u2rxie: uart2 receiver interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 13 int2ie: external interrupt 2 enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12 t5ie: timer5 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 11 t4ie: timer4 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 10 unimplemented: read as ? 0 ? bit 9 oc3ie: output compare 3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 8-5 unimplemented: read as ? 0 ? bit 4 int1ie: external interrupt 1 enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 cmie: comparator interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled
? 2011 microchip technology inc. ds39995b-page 95 pic24fv32ka304 family bit 1 mi2c1ie: master i2c1 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 si2c1ie: slave i2c1 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled register 8-12: iec1: interrupt enable control register 1 register 8-13: iec2: interrupt enable control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ic3ie ? ? ? spi2ie spf2ie bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 ic3ie: input capture channel 3 interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 4-2 unimplemented: read as ? 0 ? bit 1 spi2ie: spi2 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 spf2ie: spi2 fault interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled
pic24fv32ka304 family ds39995b-page 96 ? 2011 microchip technology inc. register 8-14: iec3: interrupt enable control register 3 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 ?rtcie ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ?mi2c2iesi2c2ie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 rtcie: real-time clock and calendar interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 13-3 unimplemented: read as ? 0 ? bit 2 mi2c2ie: master i2c2 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 si2c2ie: slave i2c2 event interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 97 pic24fv32ka304 family register 8-15: iec4: interrupt enable control register 4 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 ? ?ctmuie ? ? ? ?hlvdie bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 ? ? ? ? crcie u2erie u1erie ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ctmuie: ctmu interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 12-9 unimplemented: read as ? 0 ? bit 8 hlvdie: high/low-voltage detect interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 7-4 unimplemented: read as ? 0 ? bit 3 crcie: crc generator interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 2 u2erie: uart2 error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 1 u1erie: uart1 error interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled bit 0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 98 ? 2011 microchip technology inc. register 8-16: iec5: interrupt enable control register 5 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?ulpwuie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 unimplemented: read as ? 0 ? bit 0 ulpwuie: ultra low-power wake-up interrupt enable bit 1 = interrupt request is enabled 0 = interrupt request is not enabled
? 2011 microchip technology inc. ds39995b-page 99 pic24fv32ka304 family register 8-17: ipc0: interrupt pr iority control register 0 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t1ip2 t1ip1 t1ip0 ? oc1ip2 oc1ip1 oc1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ic1ip2 ic1ip1 ic1ip0 ? int0ip2 int0ip1 int0ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc1ip<2:0>: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic1ip<2:0>: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fv32ka304 family ds39995b-page 100 ? 2011 microchip technology inc. register 8-18: ipc1: interrupt pr iority control register 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? t2ip2 t2ip1 t2ip0 ? oc2ip2 oc2ip1 oc2ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic2ip2 ic2ip1 ic2ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 oc2ip<2:0>: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 ic2ip: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 101 pic24fv32ka304 family register 8-19: ipc2: interrupt pr iority control register 2 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u1rxip2 u1rxip1 u1rxip0 ? spi1ip2 spi1ip1 spi1ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spf1ip2 spf1ip1 spf1ip0 ? t3ip2 t3ip1 t3ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u1rxip<2:0>: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 spi1ip<2:0>: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 spf1ip<2:0>: spi1 fault interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fv32ka304 family ds39995b-page 102 ? 2011 microchip technology inc. register 8-20: ipc3: interrupt pr iority control register 3 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? nvmip2 nvmip1 nvmip0 ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? ad1ip2 ad1ip1 ad1ip0 ? u1txip2 u1txip1 u1txip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 nvmip<2:0>: nvm interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-7 unimplemented: read as ? 0 ? bit 6-4 ad1ip<2:0>: a/d conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 u1txip<2:0>: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2011 microchip technology inc. ds39995b-page 103 pic24fv32ka304 family register 8-21: ipc4: interrupt pr iority control register 4 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? cnip2 cnip1 cnip0 ?cmip2cmip1cmip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? mi2c1p2 mi2c1p1 mi2c1p0 ? si2c1p2 si2c1p1 si2c1p0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cnip<2:0>: input change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 cmip<2:0>: comparator interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 mi2c1p<2:0>: master i2c1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 si2c1p<2:0>: slave i2c1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fv32ka304 family ds39995b-page 104 ? 2011 microchip technology inc. register 8-22: ipc5: interrupt pr iority control register 5 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? int1ip2 int1ip1 int1ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2011 microchip technology inc. ds39995b-page 105 pic24fv32ka304 family register 8-23: ipc6: interrupt pr iority control register 6 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? t4ip2 t4ip1 t4ip0 ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? oc3ip2 oc3ip1 oc3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 t4ip<2:0>: timer4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-7 unimplemented: read as ? 0 ? bit 6-4 oc3ip: output compare channel 3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 106 ? 2011 microchip technology inc. register 8-24: ipc7: interrupt pr iority control register 7 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? u2txip2 u2txip1 u2txip0 ? u2rxip2 u2rxip1 u2rxip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? int2ip2 int2ip1 int2ip0 ? t5ip2 t5ip1 t5ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 u2txip<2:0>: uart2 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 u2rxip<2:0>: uart2 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 t5ip: timer5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
? 2011 microchip technology inc. ds39995b-page 107 pic24fv32ka304 family register 8-25: ipc8: interrupt pr iority control register 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? spi2ip2 spi2ip1 spi2ip0 ? spf2ip2 spf2ip1 spf2ip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 spi2ip<2:0>: spi2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as ? 0 ? bit 2-0 spf2ip<2:0>: spi2 fault interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fv32ka304 family ds39995b-page 108 ? 2011 microchip technology inc. register 8-26: ipc9: interrupt pr iority control register 9 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ic3ip2 ic3ip1 ic3ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ic3ip<2:0>: input capture channel 3 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 109 pic24fv32ka304 family register 8-27: ipc12: interrupt priority control register 12 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? mi2c2ip2 mi2c2ip1 mi2c2ip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? si2c2ip2 si2c2ip1 si2c2ip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 mi2c2ip <2:0>: master i2c2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 si2c2ip<2:0>: slave i2c2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 110 ? 2011 microchip technology inc. register 8-28: ipc15: interrupt priority control register 15 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? rtcip2 rtcip1 rtcip0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 rtcip<2:0>: real-time clock and calendar interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 111 pic24fv32ka304 family register 8-29: ipc16: interrupt priority control register 16 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 ? crcip2 crcip1 crcip0 ? u2erip2 u2erip1 u2erip0 bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? u1erip2 u1erip1 u1erip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 crcip<2:0>: crc generator error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as ? 0 ? bit 10-8 u2erip<2:0>: uart2 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as ? 0 ? bit 6-4 u1erip<2:0>: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 112 ? 2011 microchip technology inc. register 8-30: ipc18: interrupt priority control register 18 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? hlvdip2 hlvdip1 hlvdip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 hlvdip<2:0>: high/low-voltage detect interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled register 8-31: ipc19: interrupt priority control register 19 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ctmuip2 ctmuip1 ctmuip0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-7 unimplemented: read as ? 0 ? bit 6-4 ctmuip<2:0>: ctmu interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 113 pic24fv32ka304 family register 8-32: ipc20: interrupt priority control register 20 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 ? ? ? ? ? ulpwuip2 ulpwuip1 ulpwuip0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 6-4 ulpwuip<2:0>: ultra low-power wake-up interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) ? ? ? 001 = interrupt is priority 1 000 = interrupt source is disabled
pic24fv32ka304 family ds39995b-page 114 ? 2011 microchip technology inc. register 8-33: inttreg: interrupt control and status register r-0 u-0 r/w-0 u-0 r-0 r-0 r-0 r-0 cpuirq ?vhold ? ilr3 ilr2 ilr1 ilr0 bit 15 bit 8 u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ? vecnum6 vecnum5 vecnum4 vecnum3 vecnum2 vecnum1 vecnum0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cpuirq: interrupt request from interrupt controller cpu bit 1 = an interrupt request has occurred but has not yet been acknowledged by the cpu (this will happen when the cpu priority is higher than the interrupt priority) 0 = no interrupt request is left unacknowledged bit 14 unimplemented: read as ? 0 ? bit 13 vhold: vector hold bit allows vector number capture and changes what interrupt is stored in the vecnum bit. 1 = vecnum will contain the value of the highest priority pending interrupt, instead of the current interrupt 0 = vecnum will contain the value of the last acknowledged interrupt (last interrupt that has occurred with higher priority than the cpu, even if other interrupts are pending) bit 12 unimplemented: read as ? 0 ? bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 ? ? ? 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7 unimplemented: read as ? 0 ? bit 6-0 vecnum<6:0>: vector number of pending interrupt bits 0111111 = interrupt vector pending is number 135 ? ? ? 0000001 = interrupt vector pending is number 9 0000000 = interrupt vector pending is number 8
? 2011 microchip technology inc. ds39995b-page 115 pic24fv32ka304 family 8.4 interrupt setup procedures 8.4.1 initialization to configure an interrupt source: 1. set the nstdis control bit (intcon1<15>) if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate ipcx register. the priority level will depend on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate iecx register. 8.4.2 interrupt service routine the method that is used to declare an isr and initialize the ivt with the correct vector address depends on the programming language (i.e., c or assembler) and the language development toolsuite that is used to develop the application. in general, the user must clear the interrupt flag in the appropriate ifsx register for the source of the interrupt that the isr handles. otherwise, the isr will be re-entered immediately after exiting the routine. if the isr is coded in assembly language, it must be terminated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 8.4.3 trap service routine (tsr) a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 8.4.4 interrupt disable all user interrupts can be disabled using the following procedure: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value, oeh with srl. to enable user interrupts, the pop instruction may be used to restore the previous sr value. only user interrupts with a priority level of 7 or less can be disabled. trap sources (level 8-15) cannot be disabled. the disi instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized, such that all user interrupt sources are assigned to priority level 4.
pic24fv32ka304 family ds39995b-page 116 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 117 pic24fv32ka304 family 9.0 oscillator configuration the oscillator system for the pic24fv32ka304 family of devices has the following features: ? a total of five external and internal oscillator options as clock sources, providing 11 different clock modes. ? on-chip 4x phase locked loop (pll) to boost internal operating frequency on select internal and external oscillator sources. ? software-controllable switching between various clock sources. ? software-controllable postscaler for selective clocking of cpu for system power savings. ? system frequency range declaration bits for ec mode. when using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. ? a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown. a simplified diagram of the oscillator system is shown in figure 9-1 . figure 9-1: pic24fv32ka304 family clock diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on oscillator configuration, refer to the ?pic24f family reference manual? , section 38. ?oscillator with 500 khz low-power frc? (ds39726). secondary oscillator soscen enable oscillator sosco sosci clock source option for other modules osci osco primary oscillator xt, hs, ec postscaler clkdiv<10:8> wdt, pwrt, dswdt frcdiv 31 khz (nominal) 8 mhz frc lprc oscillator sosc lprc clock control logic fail-safe clock monitor frc 4 x pll xtpll, hspll ecpll,frcpll 8 mhz 4 mhz cpu peripherals postscaler clkdiv<14:12> clko reference clock generator refo refocon<15:8> oscillator 500 khz lpfrc oscillator
pic24fv32ka304 family ds39995b-page 118 ? 2011 microchip technology inc. 9.1 cpu clocking scheme the system clock source can be provided by one of four sources: ? primary oscillator (posc) on the osci and osco pins ? secondary oscillator (sosc) on the sosci and sosco pins the pic24fv32ka304 family devices consist of two types of secondary oscillator: - high-power secondary oscillator - low-power secondary oscillator these can be selected by using the soscsel (fosc<5>) bit. ? fast internal rc (frc) oscillator - 8 mhz frc oscillator - 500 khz lower power frc oscillator ? low-power internal rc (lprc) oscillator with two modes: - high-power/high accuracy mode - low-power/low accuracy mode the primary oscillator and 8 mhz frc sources have the option of using the internal 4x pll. the frequency of the frc clock source can optionally be reduced by the pro- grammable clock divider. the selected clock source generates the processor and peripheral clock sources. the processor clock source is divided by two to produce the internal instruction cycle clock, f cy . in this document, the instruction cycle clock is also denoted by f osc /2. the internal instruction cycle clock, f osc /2, can be provided on the osco i/o pin for some operating modes of the primary oscillator. 9.2 initial configuration on por the oscillator source (and operating mode) that is used at a device power-on reset (por) event is selected using configuration bit settings. the oscillator configuration bit settings are located in the configuration registers in the program memory (for more information, see section 26.1 ?configuration bits? ). the primary oscillator configuration bits, poscmd<1:0> (fosc<1:0>), and the initial oscillator select configuration bits, fnosc<2:0> (foscsel<2:0>), select the oscillator source that is used at a por. the frc primary oscillator with postscaler (frcdiv) is the default (unprogrammed) selection. the secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. the ec mode frequency range configuration bits, poscfreq<1:0> (fosc<4:3>), optimize power consumption when running in ec mode. the default configuration is ?frequency range is greater than 8mhz?. the configuration bits allow users to choose between the various clock modes, shown in tab l e 9 - 1 . 9.2.1 clock switching mode configuration bits the fcksm configuration bits (fosc<7:6>) are used jointly to configure device clock switching and the fscm. clock switching is enabled only when fcksm1 is programmed (? 0 ?). the fscm is enabled only when fcksm<1:0> are both programmed (? 00 ?). table 9-1: configuration bit va lues for clock selection oscillator mode oscillator source poscmd<1:0> fnosc<2:0> notes 8 mhz frc oscillator with postscaler (frcdiv) internal 11 111 1, 2 500 khz frc oscillator with postscaler (lpfrcdiv) internal 11 110 1 low-power rc oscillator (lprc) internal 11 101 1 secondary (timer1) oscillator (sosc) secondary 00 100 1 primary oscillator (hs) with pll module (hspll) primary 10 011 primary oscillator (ec) with pll module (ecpll) primary 00 011 primary oscillator (hs) primary 10 010 primary oscillator (xt) primary 01 010 primary oscillator (ec) primary 00 010 8 mhz frc oscillator with pll module (frcpll) internal 11 001 1 8 mhz frc oscillator (frc) internal 11 000 1 note 1: osco pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device.
? 2011 microchip technology inc. ds39995b-page 119 pic24fv32ka304 family 9.3 control registers the operation of the oscillator is controlled by three special function registers (sfrs): ? osccon ?clkdiv ?osctun the osccon register ( register 9-1 ) is the main control register for the oscillator. it controls clock source switching and allows the monitoring of clock sources. the clock divider register ( register 9-2 ) controls the features associated with doze mode, as well as the postscaler for the frc oscillator. the frc oscillator tune register ( register 9-3 ) allows the user to fine tune the frc oscillator over a range of approximately 5.25%. each bit increment or decre- ment changes the factory calibrated frequency of the frc oscillator by a fixed amount. register 9-1: osccon: os cillator control register u-0 r-0, hsc r-0, hsc r-0, hsc u-0 r/w-x (1) r/w-x (1) r/w-x (1) ? cosc2 cosc1 cosc0 ? nosc2 nosc1 nosc0 bit 15 bit 8 r/so-0, hsc u-0 r-0, hsc (2) u-0 r/co-0, hs r/w-0 (3) r/w-0 r/w-0 clklock ?lock ? cf soscdrv soscen oswen bit 7 bit 0 legend: hsc = hardware settable/clearable bit hs = hardware settable bit co = clearable only bit so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits 111 = 8 mhz fast rc oscillator with postscaler (frcdiv) 110 = 500 khz low-power fast rc oscillator (frc) with postscaler (lpfrcdiv) 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = 8 mhz frc oscillator with postscaler and pll module (frcpll) 000 = 8 mhz frc oscillator (frc) bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits (1) 111 = 8 mhz fast rc oscillator with postscaler (frcdiv) 110 = 500 khz low-power fast rc oscillator (frc) with postscaler (lpfrcdiv) 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator with pll module (xtpll, hspll, ecpll) 010 = primary oscillator (xt, hs, ec) 001 = 8 mhz frc oscillator with postscaler and pll module (frcpll) 000 = 8 mhz frc oscillator (frc) note 1: reset values for these bits are determined by the fnosc configuration bits. 2: also resets to ? 0 ? during any valid clock switch or whenever a non-pll clock mode is selected. 3: when sosc is selected to run from a digital clock input, rather than an external crystal (soscsrc = 0 ), this bit has no effect.
pic24fv32ka304 family ds39995b-page 120 ? 2011 microchip technology inc. bit 7 clklock: clock selection lock enabled bit if fscm is enabled (fcksm1 = 1 ): 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified by setting the oswen bit if fscm is disabled (fcksm1 = 0 ): clock and pll selections are never locked and may be modified by setting the oswen bit. bit 6 unimplemented: read as ? 0 ? bit 5 lock: pll lock status bit (2) 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled bit 4 unimplemented: read as ? 0 ? bit 3 cf: clock fail detect bit 1 = fscm has detected a clock failure 0 = no clock failure has been detected bit 2 soscdrv : secondary oscillator drive strength bit (3) 1 = high-power sosc circuit selected 0 = low/high-power select is done via the soscsrc configuration bit bit 1 soscen: 32 khz secondary oscillator (sosc) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to clock source specified by nosc<2:0> bits 0 = oscillator switch is complete register 9-1: osccon: oscillato r control register (continued) note 1: reset values for these bits are determined by the fnosc configuration bits. 2: also resets to ? 0 ? during any valid clock switch or whenever a non-pll clock mode is selected. 3: when sosc is selected to run from a digital clock input, rather than an external crystal (soscsrc = 0 ), this bit has no effect.
? 2011 microchip technology inc. ds39995b-page 121 pic24fv32ka304 family register 9-2: clkdiv: clock divider register r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-1 roi doze2 doze1 doze0 dozen (1) rcdiv2 rcdiv1 rcdiv0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts clear the dozen bit, and reset the cpu and peripheral clock ratio to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: cpu and peripheral clock ratio select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 dozen: doze enable bit (1) 1 = doze<2:0> bits specify the cpu and peripheral clock ratio 0 = cpu and peripheral clock ratio set to 1:1 bit 10-8 rcdiv<2:0>: frc postscaler select bits when osccon (cosc<2:0>) = 111 : 111 = 31.25 khz (divide by 256) 110 = 125 khz (divide by 64) 101 = 250 khz (divide by 32) 100 = 500 khz (divide by 16) 011 = 1 mhz (divide by 8) 010 = 2 mhz (divide by 4) 001 = 4 mhz (divide by 2) (default) 000 = 8 mhz (divide by 1) when osccon (cosc<2:0>) = 110 : 111 = 1.95 khz (divide by 256) 110 = 7.81 khz (divide by 64) 101 = 15.62 khz (divide by 32) 100 = 31.25 khz (divide by 16) 011 = 62.5 khz (divide by 8) 010 = 125 khz (divide by 4) 001 = 250 khz (divide by 2) (default) 000 = 500 khz (divide by 1) bit 7-0 unimplemented: read as ? 0 ? note 1: this bit is automatically cleared when the roi bit is set and an interrupt occurs.
pic24fv32ka304 family ds39995b-page 122 ? 2011 microchip technology inc. register 9-3: osctun: frc oscillator tune register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun5 (1) tun4 (1) tun3 (1) tun2 (1) tun1 (1) tun0 (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits (1) 011111 = maximum frequency deviation 011110 ? ? ? 000001 000000 = center frequency, oscillator is running at factory calibrated frequency 111111 ? ? ? 100001 100000 = minimum frequency deviation note 1: increments or decrements of tun<5:0> may not change the frc frequency in equal steps over the frc tuning range and may not be monotonic.
? 2011 microchip technology inc. ds39995b-page 123 pic24fv32ka304 family 9.4 clock switching operation with few limitations, applications are free to switch between any of the four clock sources (posc, sosc, frc and lprc) under software control and at any time. to limit the possible side effects that could result from this flexibility, pic24f devices have a safeguard lock built into the switching process. 9.4.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in the fosc configuration register must be programmed to ? 0 ?. (refer to section 26.0 ?special features? for further details.) if the fcksm1 configuration bit is unprogrammed (? 1 ?), the clock switching function and fscm function are disabled. this is the default setting. the noscx control bits (osccon<10:8>) do not control the clock selection when clock switching is disabled. however, the coscx bits (osccon<14:12>) will reflect the clock source selected by the fnoscx configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled; it is held at ? 0 ? at all times. 9.4.2 oscillator switching sequence at a minimum, performing a clock switch requires this basic sequence: 1. if desired, read the coscx bits (osccon<14:12>), to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the noscx bits (osccon<10:8>) for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit to initiate the oscillator switch. once the basic sequence is completed, the system clock hardware responds automatically, as follows: 1. the clock switching hardware compares the coscx bits with the new value of the noscx bits. if they are the same, then the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the lock (osccon<5>) and cf (osccon<3>) bits are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware will wait until the ost expires. if the new source is using the pll, then the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the noscx bits value is transferred to the coscx bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt, fscm or rtcc with lprc as clock source are enabled) or sosc (if soscen remains enabled). note: the primary oscillator mode has three different submodes (xt, hs and ec), which are determined by the poscmdx configuration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. note 1: the processor will continue to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes.
pic24fv32ka304 family ds39995b-page 124 ? 2011 microchip technology inc. the following code sequence for a clock switch is recommended: 1. disable interrupts during the osccon register unlock and write sequence. 2. execute the unlock sequence for the osccon high byte by writing 78h and 9ah to osccon<15:8> in two back-to-back instructions. 3. write new oscillator source to the noscx bits in the instruction immediately following the unlock sequence. 4. execute the unlock sequence for the osccon low byte by writing 46h and 57h to osccon<7:0> in two back-to-back instructions. 5. set the oswen bit in the instruction immediately following the unlock sequence. 6. continue to execute code that is not clock-sensitive (optional). 7. invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or pll to start and stabilize. 8. check to see if oswen is ? 0 ?. if it is, the switch was successful. if oswen is still set, then check the lock bit to determine the cause of failure. the core sequence for unlocking the osccon register and initiating a clock switch is shown in example 9-1 . example 9-1: basic code sequence for clock switching 9.5 reference clock output in addition to the clko output (f osc /2) available in certain oscillator modes, the device clock in the pic24fv32ka304 family devices can also be configured to provide a reference clock output signal to a port pin. this feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. this reference clock output is controlled by the refocon register ( register 9-4 ). setting the roen bit (refocon<15>) makes the clock signal available on the refo pin. the rodiv bits (refocon<11:8>) enable the selection of 16 different clock divider options. the rosslp and rosel bits (refocon<13:12>) control the availability of the reference output during sleep mode. the rosel bit determines if the oscillator on osc1 and osc2, or the current system clock source, is used for the reference clock output. the rosslp bit determines if the reference source is available on refo when the device is in sleep mode. to use the reference clock output in sleep mode, both the rosslp and rosel bits must be set. the device clock must also be configured for one of the primary modes (ec, hs or xt); otherwise, if the rosel bit is not also set, the oscillator on osc1 and osc2 will be powered down when the device enters sleep mode. clearing the rosel bit allows the reference output frequency to change as the system clock changes during any clock switches. ;place the new oscillator selection in w0 ;oscconh (high byte) unlock sequence mov #oscconh, w1 mov #0x78, w2 mov #0x9a, w3 mov.b w2, [w1] mov.b w3, [w1] ;set new oscillator selection mov.b wreg, oscconh ;oscconl (low byte) unlock sequence mov #oscconl, w1 mov #0x46, w2 mov #0x57, w3 mov.b w2, [w1] mov.b w3, [w1] ;start oscillator switch operation bset osccon,#0
? 2011 microchip technology inc. ds39995b-page 125 pic24fv32ka304 family register 9-4: refocon: reference oscillator control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 roen ? rosslp rosel rodiv3 rodiv2 rodiv1 rodiv0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 roen: reference oscillator output enable bit 1 = reference oscillator enabled on refo pin 0 = reference oscillator disabled bit 14 unimplemented: read as ? 0 ? bit 13 rosslp: reference oscillator output stop in sleep bit 1 = reference oscillator continues to run in sleep 0 = reference oscillator is disabled in sleep bit 12 rosel: reference oscillator source select bit 1 = primary oscillator used as the base clock (1) 0 = system clock used as the base clock; base clock reflects any clock switching of the device bit 11-8 rodiv<3:0>: reference oscillator divisor select bits 1111 = base clock value divided by 32,768 1110 = base clock value divided by 16,384 1101 = base clock value divided by 8,192 1100 = base clock value divided by 4,096 1011 = base clock value divided by 2,048 1010 = base clock value divided by 1,024 1001 = base clock value divided by 512 1000 = base clock value divided by 256 0111 = base clock value divided by 128 0110 = base clock value divided by 64 0101 = base clock value divided by 32 0100 = base clock value divided by 16 0011 = base clock value divided by 8 0010 = base clock value divided by 4 0001 = base clock value divided by 2 0000 = base clock value bit 7-0 unimplemented: read as ? 0 ? note 1: the crystal oscillator must be enabled using the fosc<2:0> bits; the crystal maintains the operation in sleep mode.
pic24fv32ka304 family ds39995b-page 126 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 127 pic24fv32ka304 family 10.0 power-saving features the pic24fv32ka304 family of devices provides the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. all pic24f devices manage power consumption in four different ways: ? clock frequency ? instruction-based sleep, idle and deep sleep modes ? software controlled doze mode ? selective peripheral control in software combinations of these methods can be used to selectively tailor an application?s power consumption, while still maintaining critical application features, such as timing-sensitive communications. 10.1 clock frequency and clock switching pic24f devices allow for a wide range of clock frequencies to be selected under application control. if the system clock configuratio n is not locked, users can choose low-power or high-precision oscillators by simply changing the nosc bits. the process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in section 9.0 ?oscillator configuration? . 10.2 instruction-based power-saving modes pic24f devices have two special power-saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution; idle mode halts the cpu and code execution, but allows peripheral modules to continue operation. deep sleep mode stops clock operation, code execution and all peripherals except rtcc and dswdt. it also freezes i/o states and removes power to sram and flash memory. the assembly syntax of the pwrsav instruction is shown in example 10-1 . sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to ?wake-up?. 10.2.1 sleep mode sleep mode includes these features: ? the system clock source is shut down. if an on-chip oscillator is used, it is turned off. ? the device current consumption will be reduced to a minimum provided that no i/o pin is sourcing current. ? the i/o pin directions and states are frozen. ? the fail-safe clock monitor does not operate during sleep mode since the system clock source is disabled. ? the lprc clock will continue to run in sleep mode if the wdt or rtcc with lprc as clock source is enabled. ? the wdt, if enabled, is automatically cleared prior to entering sleep mode. ? some device features, or peripherals, may continue to operate in sleep mode. this includes items, such as the input change notification on the i/o ports, or peripherals that use an external clock input. any peripheral that requires the system clock source for its operation will be disabled in sleep mode. the device will wake-up from sleep mode on any of these events: ? on any interrupt source that is individually enabled ? on any form of device reset ? on a wdt time-out on wake-up from sleep, the processor will restart with the same clock source that was active when sleep mode was entered. example 10-1: pwrsav instruction syntax note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , ?section 39. power-saving features with deep sleep? (ds39727). note: sleep_mode and idle_mode are constants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode bset dscon, #dsen ; enable deep sleep pwrsav #sleep_mode ; put the device into deep sleep mode
pic24fv32ka304 family ds39995b-page 128 ? 2011 microchip technology inc. 10.2.2 idle mode idle mode has these features: ? the cpu will stop executing instructions. ? the wdt is automatically cleared. ? the system clock source remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 10.6 ?selective peripheral module control? ). ? if the wdt or fscm is enabled, the lprc will also remain active. the device will wake from idle mode on any of these events: ? any interrupt that is individually enabled ? any device reset ? a wdt time-out on wake-up from idle, the clock is re-applied to the cpu and instruction execution begins immediately, starting with the instruction following the pwrsav instruction or the first instruction in the isr. 10.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction will be held off until entry into sleep or idle mode has completed. the device will then wake-up from sleep or idle mode. 10.2.4 deep sleep mode in pic24fv32ka304 family devices, deep sleep mode is intended to provide the lowest levels of power consumption available without requiring the use of external switches to completely remove all power from the device. entry into deep sleep mode is completely under software control. exit from deep sleep mode can be triggered from any of the following events: ? por event ?mclr event ? rtcc alarm (if the rtcc is present) ? external interrupt 0 ? deep sleep watchdog timer (dswdt) time-out ? ultra low-power wake-up (ulpwu) event in deep sleep mode, it is possible to keep the device real-time clock and calendar (rtcc) running without the loss of clock cycles. the device has a dedicated deep sleep brown-out reset (dsbor) and a deep sleep watchdog timer reset (dswdt) for monitoring voltage and time-out events. the dsbor and dswdt are independent of the standard bor and wdt used with other power-managed modes (sleep, idle and doze). 10.2.4.1 entering deep sleep mode deep sleep mode is entered by setting the dsen bit in the dscon register, and then executing a sleep command ( pwrsav #sleep_mode ). an unlock sequence is required to set the dsen bit. once the dsen bit has been set, there is no time limit before the sleep command can be executed. the dsen bit is automatically cleared when exiting the deep sleep mode. the sequence to enter deep sleep mode is: 1. if the application requires the deep sleep wdt, enable it and configure its clock source. for more information on deep sleep wdt, see section 10.2.4.5 ?deep sleep wdt? . 2. if the application requires deep sleep bor, enable it by programming the dslpbor configuration bit (fds<6>). 3. if the application requires wake-up from deep sleep on rtcc alarm, enable and configure the rtcc module for more information on rtcc, see section 19.0 ?real-time clock and calendar (rtcc)? . 4. if needed, save any critical application context data by writing it to the dsgpr0 and dsgpr1 registers (optional). 5. enable deep sleep mode by setting the dsen bit (dscon<15>). 6. enter deep sleep mode by issuing a pwrsav #0 instruction. any time the dsen bit is set, all bits in the dswake register will be automatically cleared. to set the dsen bit, the unlock sequence in example 10-2 is required: example 10-2: the unlock sequence note: to re-enter deep sleep after a deep sleep wake-up, allow a delay of at least 3 t cy after clearing the release bit. note: an unlock sequence is required to set the dsen bit. //disable interrupts for 5 instructions asm volatile(?disi #5?); //issue unlock sequence asm volatile mov #0x55, w0; mov w0, nvmkey; mov #0xaa, w1; mov w1, nvmkey; bset dscon, #dsen
? 2011 microchip technology inc. ds39995b-page 129 pic24fv32ka304 family 10.2.4.2 exiting deep sleep mode deep sleep mode exits on any one of the following events: ? por event on v dd supply. if there is no dsbor circuit to re-arm the v dd supply por circuit, the external v dd supply must be lowered to the natural arming voltage of the por circuit. ? dswdt time-out. when the dswdt timer times out, the device exits deep sleep. ? rtcc alarm (if rtcen = 1 ). ? assertion (? 0 ?) of the mclr pin. ? assertion of the int0 pin (if the interrupt was enabled before deep sleep mode was entered). the polarity configuration is used to determine the assertion level (? 0 ? or ? 1 ?) of the pin that will cause an exit from deep sleep mode. exiting from deep sleep mode requires a change on the int0 pin while in deep sleep mode. exiting deep sleep mode generally does not retain the state of the device and is equivalent to a power-on reset (por) of the device. exceptions to this include the rtcc (if present), which remains operational through the wake-up, the dsgprx registers and dswdt. wake-up events that occur after deep sleep exits but before the por sequence completes are ignored and are not be captured in the dswake register. the sequence for exiting deep sleep mode is: 1. after a wake-up event, the device exits deep sleep and performs a por. the dsen bit is cleared automatically. code execution resumes at the reset vector. 2. to determine if the device exited deep sleep, read the deep sleep bit, dpslp (rcon<10>). this bit will be set if there was an exit from deep sleep mode. if the bit is set, clear it. 3. determine the wake-up source by reading the dswake register. 4. determine if a dsbor event occurred during deep sleep mode by reading the dsbor bit (dscon<1>). 5. if application context data has been saved, read it back from the dsgpr0 and dsgpr1 registers. 6. clear the release bit (dscon<0>). 10.2.4.3 saving context data with the dsgpr0/dsgpr1 registers as exiting deep sleep mode causes a por, most special function registers reset to their default por values. in addition, because v core power is not sup- plied in deep sleep mode, information in data ram may be lost when exiting this mode. applications which require critical data to be saved prior to deep sleep may use the deep sleep general purpose registers, dsgpr0 and dsgpr1 or data eeprom (if available). unlike other sfrs, the contents of these registers are preserved while the device is in deep sleep mode. after exiting deep sleep, software can restore the data by reading the registers and clearing the release bit (dscon<0>). 10.2.4.4 i/o pins during deep sleep during deep sleep, the general purpose i/o pins retain their previous states and the secondary oscillator (sosc) will remain running, if enabled. pins that are configured as inputs (trisx bit set), prior to entry into deep sleep, remain high-impedance during deep sleep. pins that are configured as outputs (trisx bit clear), prior to entry into deep sleep, remain as output pins during deep sleep. while in this mode, they continue to drive the output level determined by their corresponding latx bit at the time of entry into deep sleep. once the device wakes back up, all i/o pins continue to maintain their previous states, even after the device has finished the por sequence and is executing application code again. pins configured as inputs during deep sleep remain high-impedance and pins configured as outputs continue to drive their previous value. after waking up, the tris and lat registers, and the soscen bit (osccon<1>) are reset. if firmware modifies any of these bits or registers, the i/o will not immediately go to the newly configured states. once the firmware clears the release bit (dscon<0>), the i/o pins are ?released?. this causes the i/o pins to take the states configured by their respective tris and lat bit values. this means that keeping the sosc running after waking up requires the soscen bit to be set before clearing release. if the deep sleep bor (dsbor) is enabled, and a dsbor or a true por event occurs during deep sleep, the i/o pins will be immediately released, similar to clearing the release bit. all previous state information will be lost, including the general purpose dsgpr0 and dsgpr1 contents. if a mclr reset event occurs during deep sleep, the dsgprx, dscon and dswake registers will remain valid, and the release bit will remain set. the state of the sosc will also be retained. the i/o pins, however, will be reset to their mclr reset state. since release is still set, changes to the soscen bit (osccon<1>) cannot take effect until the release bit is cleared. in all other deep sleep wake-up cases, application firmware must clear the release bit in order to reconfigure the i/o pins. note: any interrupt pending when entering deep sleep mode is cleared.
pic24fv32ka304 family ds39995b-page 130 ? 2011 microchip technology inc. 10.2.4.5 deep sleep wdt to enable the dswdt in deep sleep mode, program the configuration bit, dswdten (fds<7>). the device watchdog timer (wdt) need not be enabled for the dswdt to function. entry into deep sleep mode automatically resets the dswdt. the dswdt clock source is selected by the dswcksel configuration bit (fds<4>). the postscaler options are programmed by the dswdtps<3:0> configuration bits (fds<3:0>). the minimum time-out period that can be achieved is 2.1 ms and the maximum is 25.7 days. for more details on the fds configuration register and dswdt configuration options, refer to section 26.0 ?special features? . 10.2.4.6 switching clocks in deep sleep mode both the rtcc and the dswdt may run from either sosc or the lprc clock source. this allows both the rtcc and dswdt to run without requiring both the lprc and sosc to be enabled together, reducing power consumption. running the rtcc from lprc will result in a loss of accuracy in the rtcc of approximately 5 to 10%. if a more accurate rtcc is required, it must be run from the sosc clock source. the rtcc clock source is selected with the rtcosc configuration bit (fds<5>). under certain circumstances, it is possible for the dswdt clock source to be off when entering deep sleep mode. in this case, the clock source is turned on automatically (if dswdt is enabled), without the need for software intervention. however, this can cause a delay in the start of the dswdt counters. in order to avoid this delay when using sosc as a clock source, the application can activate sosc prior to entering deep sleep mode. 10.2.4.7 checking and clearing the status of deep sleep upon entry into deep sleep mode, the status bit, dpslp (rcon<10>), becomes set and must be cleared by the software. on power-up, the software should read this status bit to determine if the reset was due to an exit from deep sleep mode and clear the bit if it is set. of the four possible combinations of dpslp and por bit states, three cases can be considered: ? both the dpslp and por bits are cleared. in this case, the reset was due to some event other than a deep sleep mode exit. ? the dpslp bit is clear, but the por bit is set. this is a normal por. ? both the dpslp and por bits are set. this means that deep sleep mode was entered, the device was powered down and deep sleep mode was exited. 10.2.4.8 power-on resets ( pors ) v dd voltage is monitored to produce pors. since exiting from deep sleep functionally looks like a por, the technique described in section 10.2.4.7 ?checking and clearing the status of deep sleep? should be used to distinguish between deep sleep and a true por event. when a true por occurs, the entire device, including all deep sleep logic (deep sleep registers: rtcc, dswdt, etc.) is reset. 10.2.4.9 summary of deep sleep sequence to review, these are the necessary steps involved in invoking and exiting deep sleep mode: 1. device exits reset and begins to execute its application code. 2. if dswdt functionality is required, program the appropriate configuration bit. 3. select the appropriate clock(s) for the dswdt and rtcc (optional). 4. enable and configure the dswdt (optional). 5. enable and configure the rtcc (optional). 6. write context data to the dsgprx registers (optional). 7. enable the int0 interrupt (optional). 8. set the dsen bit in the dscon register. 9. enter deep sleep by issuing a pwrsv #sleep_mode command. 10. device exits deep sleep when a wake-up event occurs. 11. the dsen bit is automatically cleared. 12. read and clear the dpslp status bit in rcon, and the dswake status bits. 13. read the dsgprx registers (optional). 14. once all state related configurations are complete, clear the release bit. 15. application resumes normal operation.
? 2011 microchip technology inc. ds39995b-page 131 pic24fv32ka304 family register 10-1: dscon: deep sleep control register (1) r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 dsen ? ? ? ? ? ?rtccwdis bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/c-0, hs ? ? ? ? ? ulpwudis dsbor (2) release bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 dsen: deep sleep enable bit 1 = enters deep sleep on execution of pwrsav #0 0 = enters normal sleep on execution of pwrsav #0 bit 14-9 unimplemented: read as ? 0 ? bit 8 rtccwdis: rtcc wake-up disable bit 1 = wake-up from deep sleep with rtcc disabled 0 = wake-up from deep sleep with rtcc enabled bit 7-3 unimplemented: read as ?0? bit 2 ulpwudis: ulpwu wake-up disable bit 1 = wake-up from deep sleep with ulpwu disabled 0 = wake-up from deep sleep with ulpwu enabled bit 1 dsbor: deep sleep bor event bit (2) 1 = the dsbor was active and a bor event was detected during deep sleep 0 = the dsbor was not active, or was active but did not detect a bor event during deep sleep bit 0 release: i/o pin state release bit 1 = upon waking from deep sleep, i/o pins maintain their previous states to deep sleep entry 0 = release i/o pins from their state previous to deep sleep entry, and allow their respective tris and lat bits to control their states note 1: all register bits are reset only in the case of a por event outside of deep sleep mode. 2: unlike all other events, a deep sleep bor event will not cause a wake-up from deep sleep; this re-arms por.
pic24fv32ka304 family ds39995b-page 132 ? 2011 microchip technology inc. register 10-2: dswake: deep sleep wake-up source register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hs ? ? ? ? ? ? ?dsint0 bit 15 bit 8 r/w-0, hs u-0 u-0 r/w-0, hs r/w-0, hs r/w-0, hs u-0 r/w-0, hs dsflt ? ? dswdt dsrtcc dsmclr ? dspor (2,3) bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 dsint0: interrupt-on-change bit 1 = interrupt-on-change was asserted during deep sleep 0 = interrupt-on-change was not asserted during deep sleep bit 7 dsflt: deep sleep fault detect bit 1 = a fault occurred during deep sleep and some deep sleep configuration settings may have been corrupted 0 = no fault was detected during deep sleep bit 6-5 unimplemented: read as ? 0 ? bit 4 dswdt: deep sleep watchdog timer time-out bit 1 = the deep sleep watchdog timer timed out during deep sleep 0 = the deep sleep watchdog timer did not time out during deep sleep bit 3 dsrtcc: real-time clock and calendar (rtcc) alarm bit 1 = the real-time clock and calendar triggered an alarm during deep sleep 0 = the real-time clock and calendar did not trigger an alarm during deep sleep bit 2 dsmclr: mclr event bit 1 = the mclr pin was active and was asserted during deep sleep 0 = the mclr pin was not active, or was active, but not asserted during deep sleep bit 1 unimplemented: read as ? 0 ? bit 0 dspor: power-on reset event bit (2,3) 1 = the v dd supply por circuit was active and a por event was detected 0 = the v dd supply por circuit was not active, or was active but did not detect a por event note 1: all register bits are cleared when the dsen (dscon<15>) bit is set. 2: all register bits are reset only in the case of a por event outside of deep sleep mode, except bit, dspor, which does not reset on a por event that is caused due to a deep sleep exit. 3: unlike the other bits in this register, this bit can be set outside of deep sleep.
? 2011 microchip technology inc. ds39995b-page 133 pic24fv32ka304 family 10.3 ultra low-power wake-up the ultra low-power wake-up (ulpwu) on pin, rb0, allows a slow falling voltage to generate an interrupt without excess current consumption. to use this feature: 1. charge the capacitor on rb0 by configuring the rb0 pin to an output and setting it to ? 1 ?. 2. stop charging the capacitor by configuring rb0 as an input. 3. discharge the capacitor by setting the ulpen and ulpsink bits in the ulpwcon register. 4. configure sleep mode. 5. enter sleep mode. when the voltage on rb0 drops below v il , the device wakes up and executes the next instruction. this feature provides a low-power technique for periodically waking up the device from sleep mode. the time-out is dependent on the discharge time of the rc circuit on rb0. when the ulpwu module wakes the device from sleep mode, the ulpwuif bit (ifs5<0>) is set. soft- ware can check this bit upon wake-up to determine the wake-up source. see example 10-3 for initializing the ulpwu module example 10-3: ultra low-power wake-up initialization a series resistor, between rb0 and the external capacitor, provides overcurrent protection for the rb0/an0/ulpwu pin and enables software calibration of the time-out (see figure 10-1 ). figure 10-1: serial resistor a timer can be used to measure the charge time and discharge time of the capacitor. the charge time can then be adjusted to provide the desired delay in sleep. this technique compensates for the affects of temper- ature, voltage and component accuracy. the peripheral can also be configured as a simple, programmable low-voltage detect (lvd) or temperature sensor. / /******************************* // 1. charge the capacitor on rb0 //******************************* trisbbits.trisb0 = 0; latbbits.latb0 = 1; for(i = 0; i < 10000; i++) nop(); //***************************** //2. stop charging the capacitor // on rb0 //***************************** trisbbits.trisb0 = 1; //***************************** //3. enable ulpwu interrupt //***************************** ifs5bits.ulpwuif = 0; iec5bits.ulpwuie = 1; ipc21bits.ulpwuip = 0x7; //***************************** //4. enable the ultra low power // wakeup module and allow // capacitor discharge //***************************** ulpwconbits.ulpen = 1; ulpwconbit.ulpsink = 1; //***************************** //5. enter sleep mode //***************************** sleep(); //for sleep, execution will //resume here r 1 c 1 rb0
pic24fv32ka304 family ds39995b-page 134 ? 2011 microchip technology inc. register 10-3: ulpwcon: ulpwu control register (1) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 ulpen ? ulpsidl ? ? ? ? ulpsink bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ulpen: ulpwu module enable bit 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 ulpsidl: ulpwu stop in idle select bit 1 = discontinue module operation when the device enters idle mode 0 = continue module operation in idle mode bit 12-9 unimplemented: read as ? 0 ? bit 8 ulpsink: ulpwu current sink enable bit 1 = current sink is enabled 0 = current sink is disabled bit 7-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 135 pic24fv32ka304 family 10.4 voltage regulator-based power-saving features pic24fv32ka304 series devices have a voltage regulator that has the ability to alter functionality to provide power savings. the on board regulator is made up of two basic modules: the high-voltage regulator (hvreg) and the low-voltage regulator (lvreg). with the combination of hvreg and lvreg, the following power modes are available: 10.4.1 run mode in run mode, the main hvreg is providing a regulated voltage with enough current to supply a device running at full speed, and the device is not in sleep or deep sleep mode. the lvreg may or may not be running, but is unused. 10.4.2 fast wake-up sleep mode in fast wake-up sleep mode, the device is in sleep, but the main hvreg is still providing the regulated voltage at full supply current. this mode consumes the most power in sleep, but provides the fastest wake-up from sleep. 10.4.3 sleep (standby) mode in sleep mode, the device is in sleep and the main hvreg is providing a regulated voltage at a reduced (standby) supply current. this mode provides for limited functionality due to the reduced supply current. it consumes less power than fast wake-up sleep mode, but requires a longer time to wake-up from sleep. 10.4.4 low-voltage sleep mode in low-voltage sleep mode, the device is in sleep and all regulated voltage is provided solely by the lvreg. consequently, this mode provides the lowest sleep power consumption, but is also the most limited in terms of how much functionality can be enabled while in this mode. the low-voltage sleep wake-up time is longer than sleep mode due to the extra time required to raise the v core supply rail back to normal regulated levels. 10.4.5 deep sleep mode in deep sleep mode, both the main hvreg and lvreg are shut down, providing the lowest possible device power consumption. however, this mode provides no retention or functionality of the device and has the longest wake-up time. note: the pic24f32ka30x family parts do not have any internal voltage regulation, and therefore do not support low-voltage sleep mode.
pic24fv32ka304 family ds39995b-page 136 ? 2011 microchip technology inc. table 10-1: voltage regulation conf iguration settings for pic24fv32ka304 devices lvrcfg bit (fpor<2>) lvren bit (rcon<12> pmslp bit (rcon<8>) power mode during sleep description 001 fast wake-up hvreg mode (normal) is unchanged during sleep sleep lvreg is unused 000 sleep hvreg goes to low-power standby mode during sleep (standby) lvreg is unused 010 low voltage hvreg is off during sleep sleep lvreg is enabled and provides sleep voltage regulation 1x1 fast wake-up hvreg mode (normal) is unchanged during sleep sleep lvreg is disabled at all times 1x0 sleep hvreg goes to low-power standby mode during sleep (standby) lvreg is disabled at all times
? 2011 microchip technology inc. ds39995b-page 137 pic24fv32ka304 family 10.5 doze mode generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. there may be circumstances, however, where this is not practical. for example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock continues to operate from the same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default. it is also possible to use doze mode to selectively reduce power consumption in event driven applications. this allows clock-sensitive functions, such as synchronous communications, to continue without interruption. mean- while, the cpu idles, waiting for something to invoke an interrupt routine. enabling the automatic return to full-speed cpu operation on interrupts is enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. 10.6 selective peripheral module control idle and doze modes allow users to substantially reduce power consumption by slowing or stopping the cpu clock. even so, peripheral modules still remain clocked, and thus, consume power. there may be cases where the application needs what these modes do not provide: the allocation of power resources to cpu processing, with minimal power consumption from the peripherals. pic24f devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. this can be done with two control bits: ? the peripheral enable bit, generically named, ?xxxen?, located in the module?s main control sfr. ? the peripheral module disable (pmd) bit, generically named, ?xxxmd?, located in one of the pmd control registers. both bits have similar functions in enabling or disabling its associated module. setting the pmd bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. in this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect, and read values will be invalid. many peripheral modules have a corresponding pmd bit. in contrast, disabling a module by clearing its xxxen bit, disables its functionality, but leaves its registers available to be read and written to. power consumption is reduced, but not by as much as the pmd bits are used. most peripheral modules have an enable bit; exceptions include capture, compare and rtcc. to achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters idle mode. this is done through the control bit of the generic name format, ?xxxidl?. by default, all modules that can operate during idle mode will do so. using the disable on idle feature disables the module while in idle mode, allowing further reduction of power consumption during idle mode, enhancing power savings for extremely critical power applications.
pic24fv32ka304 family ds39995b-page 138 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 139 pic24fv32ka304 family 11.0 i/o ports all of the device pins (except v dd and v ss ) are shared between the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 11.1 parallel i/o (pio) ports a parallel i/o port that shares a pin with a peripheral is, in general, subservient to the peripheral. the peripheral?s output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents ?loop through?, in which a port?s digital output can drive the input of a peripheral that shares the same pin. figure 11-1 illustrates how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin may be read, but the output driver for the parallel port bit will be disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. all port pins have three registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the data latch register (latx), read the latch. writes to the latch, write the latch. reads from the port (portx), read the port pins, while writes to the port pins, write the latch. any bit and its associated data and control registers that are not valid for a particular device will be disabled. that means the corresponding latx and trisx registers, and the port pin will read as zeros. when a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other competing source of outputs. figure 11-1: block diagram of a typical shared port structure note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the i/o ports, refer to the ?pic24f family reference manual? , section 12. ?i/o ports with peripheral pin select (pps)? (ds39711). note that the pic24fv32ka304 family devices do not support peripheral pin select features. note: the i/o pins retain their state during deep sleep. they will retain this state at wake-up until the software restore bit (release) is cleared. q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 1 0 1 0 wr tris peripheral output data peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat output enable
pic24fv32ka304 family ds39995b-page 140 ? 2011 microchip technology inc. 11.1.1 open-drain configuration in addition to the port, lat and tris registers for data control, each port pin can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits configures the corresponding pin to act as an open-drain output. the maximum open-drain voltage allowed is the same as the maximum v ih specification. 11.2 configuring analog port pins the use of the ans and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. when reading the port register, all pins configured as analog input channels will read as cleared (a low level). analog levels on any pin that is defined as a digital input (including the anx pins) may cause the input buffer to consume current that exceeds the device specifications. 11.2.1 analog selection register i/o pins with shared analog functionality, such as adc inputs and comparator inputs, must have their digital inputs shut off when analog functionality is used. note that analog functionality includes an analog voltage being applied to the pin externally. to allow for analog control, the ansx registers are provided. there is one ans register for each port (ansa, ansb and ansc). within each ansx register, there is a bit for each pin that shares analog functionality with the digital i/o functionality. if a particular pin does not have an analog function, that bit is unimplemented. see register 11-1 to register 11-3 for implementation. register 11-1: ansa: analog selection (porta) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? ansa3 ansa2 ansa1 ansa0 bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-4 unimplemented: read as ? 0 ? bit 3-0 ansa<3:0>: analog select control bits 1 = digital input buffer is not active (use for analog input) 0 = digital input buffer is active
? 2011 microchip technology inc. ds39995b-page 141 pic24fv32ka304 family register 11-2: ansb: analog selection (portb) r/w-1 r/w-1 r/w-1 r/w-1 u-0 u-0 u-0 u-0 ansb15 ansb14 ansb13 ansb12 ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ansb4 ansb3 (1) ansb2 ansb1 ansb0 bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-12 ansb<15:12>: analog select control bits 1 = digital input buffer is not active (use for analog input) 0 = digital input buffer is active bit 11-5 unimplemented: read as ? 0 ? bit 4-0 ansb<4:0>: analog select control bits 1 = digital input buffer is not active (use for analog input) 0 = digital input buffer is active note 1: not available on 20-pin devices. register 11-3: ansc analog selection (portc) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 ? ? ? ? ? ansc2 (1) ansc1 (1) ansc0 (1) bit 7 bit 0 legend: u = unimplemented bit, read as ?0? r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as ? 0 ? bit 2-0 ansc<2:0>: analog select control bits 1 = digital input buffer not active (use for analog input) 0 = digital input buffer active note 1: not available on 20-pin or 28-pin devices.
pic24fv32ka304 family ds39995b-page 142 ? 2011 microchip technology inc. 11.2.2 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically, this instruction would be a nop . 11.3 input change notification the input change notification function of the i/o ports allows the pic24fv32ka304 family of devices to generate interrupt requests to the processor in response to a change-of-state (cos) on selected input pins. this feature is capable of detecting input change of states, even in sleep mode, when the clocks are disabled. depending on the device pin count, there are up to 23 external signals (cn0 through cn22) that may be selected (enabled) for generating an interrupt request on a change-of-state. there are six control registers associated with the cn module. the cnen1 and cnen2 registers contain the interrupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin also has a weak pull-up/pull-down connected to it. the pull-ups act as a current source that is connected to the pin. the pull-downs act as a current sink to eliminate the need for external resistors when push button or keypad devices are connected. on any pin, only the pull-up resistor or the pull-down resistor should be enabled, but not both of them. if the push button or the keypad is connected to v dd , enable the pull-down, or if they are connected to v ss , enable the pull-up resistors. the pull-ups are enabled separately using the cnpu1 and cnpu2 registers, which contain the control bits for each of the cn pins. setting any of the control bits enables the weak pull-ups for the corresponding pins. the pull-downs are enabled separately, using the cnpd1 and cnpd2 registers, which contain the control bits for each of the cn pins. setting any of the control bits enables the weak pull-downs for the corresponding pins. when the internal pull-up is selected, the pin uses v dd as the pull-up source voltage. when the internal pull-down is selected, the pins are pulled down to v ss by an internal resistor. make sure that there is no external pull-up source/pull-down sink when the internal pull-ups/pull-downs are enabled. example 11-1: port write/read example note: pull-ups and pull-downs on change notifi- cation pins should always be disabled whenever the port pin is configured as a digital output. mov 0xff00, w0; //configure portb<15:8> as inputs and portb<7:0> as outputs mov w0, trisb; nop; //delay 1 cycle btss portb, #13; //next instruction equivalent ?c? code trisb = 0xff00; //configure portb<15:8> as inputs and portb<7:0> as outputs nop(); //delay 1 cycle if(portbbits.rb13 == 1) // execute following code if portb pin 13 is set. { }
? 2011 microchip technology inc. ds39995b-page 143 pic24fv32ka304 family 12.0 timer1 the timer1 module is a 16-bit timer which can serve as the time counter for the real-time clock (rtc), or operate as a free-running, interval timer/counter. timer1 can operate in three modes: ? 16-bit timer ? 16-bit synchronous counter ? 16-bit asynchronous counter timer1 also supports these features: ? timer gate operation ? selectable prescaler settings ? timer operation during cpu idle and sleep modes ? interrupt on 16-bit period register match or falling edge of external gate signal figure 12-1 illustrates a block diagram of the 16-bit timer1 module. to configure timer1 for operation: 1. set the ton bit (= 1 ). 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. set or clear the tsync bit to configure synchronous or asynchronous operation. 5. load the timer period value into the pr1 register. 6. if interrupts are required, set the interrupt enable bit, t1ie. use the priority bits, t1ip<2:0>, to set the interrupt priority. figure 12-1: 16-bit time r1 module block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive refer- ence source. for more information on timers, refer to the ?pic24f family refer- ence manual? , section 14. ?timers? (ds39704). ton sync sosci sosco/ pr1 set t1if equal comparator tmr1 reset soscen 1 0 tsync q q d ck tckps<1:0> prescaler 1, 8, 64, 256 2 tgate t cy 1 0 t1ck tcs 1x 01 tgate 00 gate sync
pic24fv32ka304 family ds39995b-page 144 ? 2011 microchip technology inc. register 12-1: t1con: ti mer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 ton ?tsidl ? ? ?t1ecs1 (1) t1ecs0 (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 ? tgate tckps1 tckps0 ?tsynctcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9-8 t1ecs <1:0>: timer1 extended clock select bits (1) 11 = reserved; do not use 10 = timer1 uses lprc as the clock source 01 = timer1 uses external clock from t1ck 00 = timer1 uses secondary oscillator (sosc) as the clock source bit 7 unimplemented: read as ? 0 ? bit 6 tgate: timer1 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as ? 0 ? bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronize external clock input 0 = do not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = timer1 clock source selected by t1ecs<1:0> 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: the t1ecs bits are valid only when tcs = 1 .
? 2011 microchip technology inc. ds39995b-page 145 pic24fv32ka304 family 13.0 timer2/3 and timer4/5 the timer2/3 and timer4/5 modules are 32-bit timers, which can also be configured as four independent,16-bit timers with selectable operating modes. as a 32-bit timer, timer2/3 or timer4/5 operate in three modes: ? two independent 16-bit timers (timer2 and timer3) with all 16-bit operating modes (except asynchronous counter mode) ? single 32-bit timer ? single 32-bit synchronous counter they also support these features: ? timer gate operation ? selectable prescaler settings ? timer operation during idle and sleep modes ? interrupt on a 32-bit period register match ? adc event trigger individually, all four of the 16-bit timers can function as synchronous timers or counters. they also offer the features listed above, except for the adc event trigger (this is implemented only with timer3). the operating modes and enabled features are determined by setting the appropriate bit(s) in the t2con, t3con, t4con, and t5con registers. t2con,t3con, t4con, and t5con are provided in generic form in register 13-1 and register 13-2 , respectively. for 32-bit timer/counter operation, timer2/timer4 is the least significant word (lsw) and timer3 / timer 5 is the most significant word (msw) of the 32-bit timer. to configure timer2/3 or timer4/5 for 32-bit operation: 1. set the t32 bit (t2con<3> or t4con<3> = 1 ). 2. select the prescaler ratio for timer2 or timer4 using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. load the timer period value. pr3 (or pr5) will contain the most significant word of the value while pr2 (or pr4) contains the least significant word. 5. if interrupts are required, set the interrupt enable bit, txie. use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton bit (txcon<15> = 1 ). the timer value, at any point, is stored in the register pair, tmr3:tmr2 (or tmr5:tmr4). tmr3 (tmr5) always contains the most significant word of the count, while tmr2 (tmr4) contains the least significant word. to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer (t2con<3> for timer2 and timer3 or t4con<3> for timer4 and timer5). 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. load the timer period value into the prx register. 5. if interrupts are required, set the interrupt enable bit, txie; use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton bit (txcon<15> = 1 ). note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on timers, refer to the ?pic24f family reference manual? , section 14. ?timers? (ds39704). note: for 32-bit operation, t3con or t5con control bits are ignored. only t2con or t4con control bits are used for setup and control. timer2 or timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the timer3 or timer5 interrupt flags.
pic24fv32ka304 family ds39995b-page 146 ? 2011 microchip technology inc. figure 13-1: timer2/3 and timer4/5 (32-bit) block diagram tmr3 tmr2 set t3if (t5if) equal comparator pr3 pr2 reset lsb msb note 1: the 32-bit timer configuration bit, t32, must be set fo r 32-bit timer/counter operation. all control bits are respective to the t2con and t4con registers. 2: the adc event trigger is available only on timer2/3 in 32-bit mode and timer3 in 16-bit mode. data bus<15:0> tmr3hld read tmr2 (tmr4) (1) write tmr2 (tmr4) (1) 16 16 16 q qd ck tgate 0 1 ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs tgate gate t2ck sync adc event trigger (2) sync (t4ck) (pr5) (pr4) (tmr5hld) (tmr5) (tmr4) 1x 01 00
? 2011 microchip technology inc. ds39995b-page 147 pic24fv32ka304 family figure 13-2: timer2 and timer4 (16-bit synchronous) block diagram figure 13-3: timer3 and timer5 (16-bit asynchronous) block diagram ton tckps<1:0> prescaler 1, 8, 64, 256 2 t cy tcs 1x 01 tgate 00 gate t2ck sync pr2 (pr4) set t2if (t4if) equal comparator tmr2 (tmr4) reset q qd ck tgate 1 0 (t4ck) sync ton tckps<1:0> 2 t cy tcs 1x 01 tgate 00 t3ck pr3 (pr5) set t3if (t5if) equal comparator tmr3 (tmr5) reset q qd ck tgate 1 0 adc event trigger (1) (t5ck) prescaler 1, 8, 64, 256 sync note 1: the adc event trigger is available only on timer3.
pic24fv32ka304 family ds39995b-page 148 ? 2011 microchip technology inc. register 13-1: txcon: timer2 and timer4 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton ?tsidl ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 ? tgate tckps1 tckps0 t32 (1) ?tcs ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timer2 on bit when txcon<3> = 1 : 1 = starts 32-bit timerx/y 0 = stops 32-bit timerx/y when txcon<3> = 0 : 1 = starts 16-bit timerx 0 = stops 16-bit timerx bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timerx input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 t32: 32-bit timer mode select bit (1) 1 = timer2 and timer3 or timer4 and timer5 form a single 32-bit timer 0 = timer2 and timer3 or timer4 and timer5 act as two 16-bit timers bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timerx clock source select bit 1 = external clock from pin, txck (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: in 32-bit mode, the t3con or t5con control bits do not affect 32-bit timer operation.
? 2011 microchip technology inc. ds39995b-page 149 pic24fv32ka304 family register 13-2: tycon: timer3 and timer5 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton (1) ?tsidl (1) ? ? ? ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 ?tgate (1) tckps1 (1) tckps0 (1) ? ?tcs (1) ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ton: timery on bit (1) 1 = starts 16-bit timery 0 = stops 16-bit timery bit 14 unimplemented: read as ? 0 ? bit 13 tsidl: stop in idle mode bit (1) 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as ? 0 ? bit 6 tgate: timery gated time accumulation enable bit (1) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 5-4 tckps<1:0>: timery input clock prescale select bits (1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 unimplemented: read as ? 0 ? bit 1 tcs: timery clock source select bit (1) 1 = external clock from the t3ck pin (on the rising edge) 0 = internal clock (f osc /2) bit 0 unimplemented: read as ? 0 ? note 1: when 32-bit operation is enabled (txcon<3> = 1 ), these bits have no effect on timery operation. all timer functions are set through txcon.
pic24fv32ka304 family ds39995b-page 150 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 151 pic24fv32ka304 family 14.0 input capture with dedicated timers all devices in the pic24fv32ka304 family features 3 independent input capture modules. each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. key features of the input capture module include: ? hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules ? synchronous and trigger modes of output compare operation, with up to 20 user-selectable trigger/sync sources available ? a 4-level fifo buffer for capturing and holding timer values for several events ? configurable interrupt generation ? up to 6 clock sources available for each module, driving a separate internal 16-bit counter the module is controlled through two registers: icxcon1 ( register 14-1 ) and icxcon2 ( register 14-2 ). a general block diagram of the module is shown in figure 14-1 . 14.1 general operating modes 14.1.1 synchronous and trigger modes by default, the input capture module operates in a free-running mode. the internal 16-bit counter, icxtmr, counts up continuously, wrapping around from ffffh to 0000h on each overflow, with its period synchronized to the selected external clock source. when a capture event occurs, the current 16-bit value of the internal counter is written to the fifo buffer. in synchronous mode, the module begins capturing events on the icx pin as soon as its selected clock source is enabled. whenever an event occurs on the selected sync source, the internal counter is reset. in trigger mode, the module waits for a sync event from another internal module to occur before allowing the internal counter to run. standard, free-running operation is selected by setting the syncsel bits to ? 00000 ? and clearing the ictrig bit (icxcon2<7>). synchronous and trigger modes are selected any time the syncsel bits are set to any value except ? 00000 ?. the ictrig bit selects either synchronous or trigger mode; setting the bit selects trigger mode operation. in both modes, the syncsel bits determine the sync/trigger source. when the syncsel bits are set to ? 00000 ? and ictrig is set, the module operates in software trigger mode. in this case, capture operations are started by manually setting the trigstat bit (icxcon2<6>). figure 14-1: input capture block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 34. ?input capture with dedicated timer? (ds39722). icxbuf 4-level fifo buffer icx pin icm<2:0> set icxif edge detect logic ici<1:0> icov, icbne interrupt logic system bus prescaler counter 1:1/4/16 and clock synchronizer event and trigger and sync logic clock select ic clock sources trigger and sync sources ictsel<2:0> syncsel<4:0> trigger 16 16 16 icxtmr increment reset
pic24fv32ka304 family ds39995b-page 152 ? 2011 microchip technology inc. 14.1.2 cascaded (32-bit) mode by default, each module operates independently with its own 16-bit timer. to increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (for example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) the odd-numbered module (icx) provides the least signif- icant 16 bits of the 32-bit register pairs, and the even module (icy) provides the most significant 16 bits. wrap arounds of the icx registers cause an increment of their corresponding icy registers. cascaded operation is configured in hardware by setting the ic32 bit (icxcon2<8>) for both modules. 14.2 capture operations the input capture module can be configured to capture timer values and generate interrupts on rising edges on icx, or all transitions on icx. captures can be configured to occur on all rising edges or just some (every 4th or 16th). interrupts can be independently configured to generate on each event or a subset of events. to set up the module for capture operations: 1. if synchronous mode is to be used, disable the sync source before proceeding. 2. make sure that any previous data has been removed from the fifo by reading icxbuf until the icbne bit (icxcon1<3>) is cleared. 3. set the syncsel bits (icxcon2<4:0>) to the desired sync/trigger source. 4. set the ictsel bits (icxcon1<12:10>) for the desired clock source. if the desired clock source is running, set the ictsel bits before the input capture module is enabled for proper synchronization with the desired clock source. 5. set the ici bits (icxcon1<6:5>) to the desired interrupt frequency. 6. select synchronous or trigger mode operation: a) check that the syncsel bits are not set to ? 00000 ?. b) for synchronous mode, clear the ictrig bit (icxcon2<7>). c) for trigger mode, set ictrig and clear the trigstat bit (icxcon2<6>). 7. set the icm bits (icxcon1<2:0>) to the desired operational mode. 8. enable the selected trigger/sync source. for 32-bit cascaded operations, the setup procedure is slightly different: 1. set the ic32 bits for both modules (icycon2<8> and (icxcon2<8>), enabling the even-numbered module first. this ensures the modules will start functioning in unison. 2. set the ictsel and syncsel bits for both modules to select the same sync/trigger and time base source. set the even module first, then the odd module. both modules must use the same ictsel and syncsel settings. 3. clear the ictrig bit of the even module (icycon2<7>). this forces the module to run in synchronous mode with the odd module, regardless of its trigger setting. 4. use the odd module?s ici bits (icxcon1<6:5>) to the desired interrupt frequency. 5. use the ictrig bit of the odd module (icxcon2<7>) to configure trigger or synchronous mode operation. 6. use the icm bits of the odd module (icxcon1<2:0>) to set the desired capture mode. the module is ready to capture events when the time base and the trigger/sync source are enabled. when the icbne bit (icxcon1<3>) becomes set, at least one capture value is available in the fifo. read input capture values from the fifo until the icbne clears to ? 0 ?. for 32-bit operation, read both the icxbuf and icybuf for the full 32-bit timer value (icxbuf for the lsw, icybuf for the msw). at least one capture value is available in the fifo buffer when the odd module?s icbne bit (icxcon1<3>) becomes set. continue to read the buffer registers until icbne is cleared (performed automatically by hardware). note: for synchronous mode operation, enable the sync source as the last step. both input capture modules are held in reset until the sync source is enabled.
? 2011 microchip technology inc. ds39995b-page 153 pic24fv32ka304 family register 14-1: icxcon1: input capture x control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 ? ? icsidl ictsel2 ictsel1 ictsel0 ? ? bit 15 bit 8 u-0 r/w-0 r/w-0 r-0, hcs r-0, hcs r/w-0 r/w-0 r/w-0 ? ici1 ici0 icov icbne icm2 (1) icm1 (1) icm0 (1) bit 7 bit 0 legend: hcs = hardware clearable/settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 icsidl: input capture x module stop in idle control bit 1 = input capture module halts in cpu idle mode 0 = input capture module continues to operate in cpu idle mode bit 12-10 ictsel<2:0>: input capture timer select bits 111 = system clock (f osc /2) 110 = reserved 101 = reserved 100 =timer1 011 =timer5 010 =timer4 001 =timer2 000 =timer3 bit 9-7 unimplemented: read as ? 0 ? bit 6-5 ici<1:0>: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture x overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture x buffer empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits (1) 111 = interrupt mode: input capture functions as interrupt pin only when device is in sleep or idle mode (rising edge detect only, all other control bits are not applicable) 110 = unused (module disabled) 101 = prescaler capture mode: capture on every 16th rising edge 100 = prescaler capture mode: capture on every 4th rising edge 011 = simple capture mode: capture on every rising edge 010 = simple capture mode: capture on every falling edge 001 = edge detect capture mode: capture on every edge (rising and falling); ici<1:0 bits do not control interrupt generation for this mode 000 = input capture module is turned off
pic24fv32ka304 family ds39995b-page 154 ? 2011 microchip technology inc. register 14-2: icxcon2: input capture x control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?ic32 bit 15 bit 8 r/w-0 r/w-0, hs u-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 ictrig trigstat ? syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 ic32: cascade two ic modules enable bit (32-bit operation) 1 = icx and icy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = icx functions independently as a 16-bit module bit 7 ictrig: icx trigger/sync select bit 1 = trigger icx from source designated by syncselx bits 0 = synchronize icx with source designated by syncselx bits bit 6 trigstat: timer trigger status bit 1 = timer source has been triggered and is running (set in hardware, can be set in software) 0 = timer source has not been triggered and is being held clear bit 5 unimplemented: read as ? 0 ? bit 4-0 syncsel<4:0>: trigger/synchronization source selection bits 11111 = reserved 11110 = reserved 11101 = reserved 11100 = ctmu (1) 11011 = a/d (1) 11010 = comparator 3 (1) 11001 = comparator 2 (1) 11000 = comparator 1 (1) 10111 = input capture 4 10110 = input capture 3 10101 = input capture 2 10100 = input capture 1 10011 = reserved 10010 = reserved 1000x = reserved 01111 = timer5 01110 = timer4 01101 = timer3 01100 = timer2 01011 = timer1 01010 = input capture 5 01001 = reserved 01000 = reserved 00111 = reserved 00110 = reserved 00101 = output compare 5 00100 = output compare 4 00011 = output compare 3 00010 = output compare 2 00001 = output compare 1 00000 = not synchronized to any other module note 1: use these inputs as trigger sources only and never as sync sources.
? 2011 microchip technology inc. ds39995b-page 155 pic24fv32ka304 family 15.0 output compare with dedicated timers all devices in the pic24fv32ka304 family feature 3 independent output compare modules. each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events. also, the modules can produce pulse-width modulated (pwm) waveforms for driving power applications. key features of the output compare module include: ? hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules ? synchronous and trigger modes of output compare operation, with up to 21 user-selectable trigger/sync sources available ? two separate period registers (a main register, ocxr, and a secondary register, ocxrs) for greater flexibility in generating pulses of varying widths ? configurable for single pulse or continuous pulse generation on an output event, or continuous pwm waveform generation ? up to 6 clock sources available for each module, driving a separate internal 16-bit counter 15.1 general operating modes 15.1.1 synchronous and trigger modes by default, the output compare module operates in a free-running mode. the internal 16-bit counter, ocxtmr, counts up continuously, wrapping around from ffffh to 0000h on each overflow, with its period synchronized to the selected external clock source. compare or pwm events are generated each time a match between the internal counter and one of the period registers occurs. in synchronous mode, the module begins performing its compare or pwm operation as soon as its selected clock source is enabled. whenever an event occurs on the selected sync source, the module?s internal counter is reset. in trigger mode, the module waits for a sync event from another internal module to occur before allowing the counter to run. free-running mode is selected by default, or any time that the syncsel bits (ocxcon2<4:0>) are set to ? 00000 ?. synchronous or trigger modes are selected any time the syncsel bits are set to any value except ? 00000 ?. the octrig bit (ocxcon2<7>) selects either synchronous or trigger mode. setting this bit selects trigger mode operation. in both modes, the syncsel bits determine the sync/trigger source. 15.1.2 cascaded (32-bit) mode by default, each module operates independently with its own set of 16-bit timer and duty cycle registers. to increase the range, adjacent even and odd modules can be configured to function as a single 32-bit module. (for example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) the odd-numbered module (ocx) provides the least significant 16 bits of the 32-bit register pairs, and the even-numbered module (ocy) provides the most significant 16 bits. wrap arounds of the ocx registers cause an increment of their corresponding ocy registers. cascaded operation is configured in hardware by setting the oc32 bit (ocxcon2<8>) for both modules. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 35. ?output compare with dedicated timer? (ds39723).
pic24fv32ka304 family ds39995b-page 156 ? 2011 microchip technology inc. figure 15-1: output compare block diagram (16-bit mode) ocxr comparator ocxtmr ocxcon1 ocxcon2 oc output and ocx interrupt ocx pin ocxrs comparator fault logic match event match event trigger and sync logic clock select increment reset oc clock sources trigger and sync sources reset match event octselx syncselx trigstat trigmode octrig ocmx ocinv octris fltout flttrien fltmd enfltx ocfltx dcbx ocfa/ ocfb/ cxout
? 2011 microchip technology inc. ds39995b-page 157 pic24fv32ka304 family 15.2 compare operations in compare mode ( figure 15-1 ), the output compare module can be configured for single-shot or continuous pulse generation. it can also repeatedly toggle an output pin on each timer event. to set up the module for compare operations: 1. calculate the required values for the ocxr and (for double compare modes) ocxrs duty cycle registers: a) determine the instruction clock cycle time. take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. b) calculate time to the rising edge of the output pulse relative to the timer start value (0000h). c) calculate the time to the falling edge of the pulse based on the desired pulse width, and the time to the rising edge of the pulse. 2. write the rising edge value to ocxr and the falling edge value to ocxrs. 3. for trigger mode operations, set octrig to enable trigger mode. set or clear trigmode to configure trigger operation and trigstat to select a hardware or software trigger. for synchronous mode, clear octrig. 4. set the syncsel<4:0> bits to configure the trigger or synchronization source. if free-running timer operation is required, set the syncsel bits to ? 00000 ? (no sync/trigger source). 5. select the time base source with the octsel<2:0> bits. if the desired clock source is running, set the octsel<2:0> bits before the output compare module is enabled for proper synchronization with the desired clock source. if necessary, set the ton bit for the selected timer which enables the compare time base to count. synchronous mode operation starts as soon as the synchronization source is enabled; trigger mode operation starts after a trigger source event occurs. 6. set the ocm<2:0> bits for the appropriate compare operation (? 0xx ?). for 32-bit cascaded operation, these steps are also necessary: 1. set the oc32 bits for both registers (ocycon2<8> and (ocxcon2<8>). enable the even-numbered module first to ensure the modules will start functioning in unison. 2. clear the octrig bit of the even module (ocycon2), so the module will run in synchronous mode. 3. configure the desired output and fault settings for ocy. 4. force the output pin for ocx to the output state by clearing the octris bit. 5. if trigger mode operation is required, configure the trigger options in ocx by using the octrig (ocxcon2<7>), trigstat (ocxcon2<6>) and syncsel (ocxcon2<4:0>) bits. 6. configure the desired compare or pwm mode of operation (ocm<2:0>) for ocy first, then for ocx. depending on the output mode selected, the module holds the ocx pin in its default state and forces a transition to the opposite state when ocxr matches the timer. in double compare modes, ocx is forced back to its default state when a match with ocxrs occurs. the ocxif interrupt flag is set after an ocxr match in single compare modes and after each ocxrs match in double compare modes. single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the ocxcon1 register. continuous pulse events continue indefinitely until terminated.
pic24fv32ka304 family ds39995b-page 158 ? 2011 microchip technology inc. 15.3 pulse-width modulation (pwm) mode in pwm mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. all pwm operations are double-buffered (buffer registers are internal to the module and are not mapped into sfr space). to configure the output compare module for edge-aligned pwm operation: 1. calculate the desired on-time and load it into the ocxr register. 2. calculate the desired period and load it into the ocxrs register. 3. select the current ocx as the synchronization source by writing 0x1f to syncsel<4:0> (ocxcon2<4:0>) and ? 0 ? to octrig (ocxcon2<7>). 4. select a clock source by writing the octsel2<2:0> (ocxcon<12:10>) bits. 5. enable interrupts, if required, for the timer and output compare modules. the output compare interrupt is required for pwm fault pin utilization. 6. select the desired pwm mode in the ocm<2:0> (ocxcon1<2:0>) bits. 7. if a timer is selected as a clock source, set the tmry prescale value and enable the time base by setting the ton (txcon<15>) bit. figure 15-2: output compare block diagram (double-buffered, 16-bit pwm mode) ocxr and dcb<1:0> buffers comparator ocxtmr ocxcon1 ocxcon2 oc output timing ocx interrupt ocx pin ocxrs buffer comparator and fault logic match match trigger and sync logic clock select increment reset oc clock sources trigger and sync sources reset match event ocfa/ocfb/cxout octselx syncselx trigstat trigmode octrig ocmx ocinv octris fltout flttrien fltmd enfltx ocfltx ocxr and dcb<1:0> ocxrs event event rollover rollover/reset rollover/reset dcb<1:0>
? 2011 microchip technology inc. ds39995b-page 159 pic24fv32ka304 family 15.3.1 pwm period in edge-aligned pwm mode, the period is specified by the value of the ocxrs register. in center-aligned pwm mode, the period of the synchronization source, such as the timers? pry, specifies the period. the period in both cases can be calculated using equation 15-1 . equation 15-1: calculating the pwm period (1) 15.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ocxrs and ocxr registers. the ocxrs and ocxr registers can be written to at any time, but the duty cycle value is not latched until a period is complete. this provides a double buffer for the pwm duty cycle and is essential for glitchless pwm operation. some important boundary parameters of the pwm duty cycle include: ? edge-aligned pwm: - if ocxr and ocxrs are loaded with 0000h, the ocx pin will remain low (0% duty cycle). - if ocxrs is greater than ocxr, the pin will remain high (100% duty cycle). ? center-aligned pwm (with tmry as the sync source): - if ocxr, ocxrs and pry are all loaded with 0000h, the ocx pin will remain low (0% duty cycle). - if ocxrs is greater than pry, the pin will go high (100% duty cycle). see example 15-3 for pwm mode timing details. table 15-1 and ta bl e 1 5 -2 show example pwm frequencies and resolutions for a device operating at 4 mips and 10 mips, respectively. equation 15-2: calculation for maximum pwm resolution (1) equation 15-3: pwm period and duty cycle calculations (1) pwm period = [value + 1] x t cy x (prescaler value) where: note 1: based on t cy = t osc * 2; doze mode and pll are disabled. (if tmry is the sync source). and can be pry in center- aligned pwm mode value = ocxrs in edge-aligned pwm mode ( ) maximum pwm resolution (bits) = f cy f pwm ? (prescale value) log 10 log 10 (2) bits note 1: based on f cy = f osc /2, doze mode and pll are disabled. 1. find the ocxrs register value for a desired pwm frequency of 52.08 khz, where f osc = 8 mhz with pll (32 mhz device clock rate) and a prescaler setting of 1:1 using edge-aligned pwm mode: t cy = 2 * t osc = 62.5 ns pwm period = 1/pwm frequency = 1/52.08 khz = 19.2 ? s pwm period = (ocxrs + 1) ? t cy ? (ocx prescale value) 19.2 ? s = (ocxrs + 1) ? 62.5 ns ? 1 ocxrs = 306 2. find the maximum resolution of the duty cycle that can be used with a 52.08 khz frequency and a 32 mhz device clock rate: pwm resolution = log 10 (f cy /f pwm )/log 10 2) bits =(log 10 (16 mhz/52.08 khz)/log 10 2) bits = 8.3 bits note 1: based on t cy = 2 * t osc ; doze mode and pll are disabled.
pic24fv32ka304 family ds39995b-page 160 ? 2011 microchip technology inc. 15.4 subcycle resolution the dcb bits (ocxcon2<10:9>) provide for resolution better than one instruction cycle. when used, they delay the falling edge generated from a match event by a portion of an instruction cycle. for example, setting dcb<1:0> = 10 causes the falling edge to occur halfway through the instruction cycle in which the match event occurs, instead of at the beginning. these bits cannot be used when ocm<2:0> = 001 . when operating the module in pwm mode (ocm<2:0> = 110 or 111 ), the dcb bits will be double-buffered. the dcb bits are intended for use with a clock source identical to the system clock. when an ocx module with enabled prescaler is used, the falling edge delay caused by the dcb bits will be referenced to the system clock period rather than the ocx module?s period. table 15-1: example pwm frequencies and resolutions at 4 mips (f cy = 4 mhz) (1) table 15-2: example pwm frequencies and resolutions at 16 mips (f cy = 16 mhz) (1) pwm frequency 7.6 hz 61 hz 122 hz 977 hz 3.9 khz 31.3 khz 125 khz prescaler ratio 8111111 period value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 note 1: based on f cy = f osc /2; doze mode and pll are disabled. pwm frequency 30.5 hz 244 hz 488 hz 3.9 khz 15.6 khz 125 khz 500 khz prescaler ratio 8111111 period value ffffh ffffh 7fffh 0fffh 03ffh 007fh 001fh resolution (bits) 16 16 15 12 10 7 5 note 1: based on f cy = f osc /2; doze mode and pll are disabled.
? 2011 microchip technology inc. ds39995b-page 161 pic24fv32ka304 family register 15-1: ocxcon1: output compare x control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ocsidl octsel2 octsel1 octsel0 enflt2 enflt1 bit 15 bit 8 r/w-0 r/w-0, hcs r/w-0, hcs r/w-0, hcs r/w-0 r/w-0 r/w-0 r/w-0 enflt0 ocflt2 ocflt1 ocflt0 trigmode ocm2 (1) ocm1 (1) ocm0 (1) bit 7 bit 0 legend: hcs = hardware clearable/settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 ocsidl: stop output compare x in idle mode control bit 1 = output compare x halts in cpu idle mode 0 = output compare x continues to operate in cpu idle mode bit 12-10 octsel<2:0>: output compare x timer select bits 111 = system clock 110 = reserved 101 = reserved 100 = timer1 011 = timer5 010 = timer4 001 = timer3 000 = timer2 bit 9 enflt2: comparator fault input enable bit (2) 1 = comparator fault input is enabled 0 = comparator fault input is disabled bit 8 enflt1: ocfb fault input enable bit 1 = ocfb fault input is enabled 0 = ocfb fault input is disabled bit 7 enflt0: ocfa fault input enable bit 1 = ocfa fault input is enabled 0 = ocfa fault input is disabled bit 6 ocflt2: pwm comparator fault condition status bit (2) 1 = pwm comparator fault condition has occurred (this is cleared in hardware only) 0 = pwm comparator fault condition has not occurred (this bit is used only when ocm<2:0> = 111 ) bit 5 ocflt1: pwm ocfb fault input enable bit 1 = pwm ocfb fault condition has occurred (this is cleared in hardware only) 0 = pwm ocfb fault condition has not occurred (this bit is used only when ocm<2:0> = 111 ) bit 4 ocflt0: pwm ocfa fault condition status bit 1 = pwm ocfa fault condition has occurred (this is cleared in hardware only) 0 = pwm ocfa fault condition has not occurred (this bit is used only when ocm<2:0> = 111 ) bit 3 trigmode: trigger status mode select bit 1 = trigstat (ocxcon2<6>) is cleared when ocxrs = ocxtmr or in software 0 = trigstat is only cleared by software note 1: the comparator module used for fault input varies with the ocx module. oc1 and oc2 use comparator 1; oc3 and oc4 use comparator 2; oc5 uses comparator 3.
pic24fv32ka304 family ds39995b-page 162 ? 2011 microchip technology inc. bit 2-0 ocm<2:0>: output compare x mode select bits (1) 111 = center-aligned pwm mode on ocx 110 = edge-aligned pwm mode on ocx 101 = double compare continuous pulse mode: initialize ocx pin low, toggle ocx state continuously on alternate matches of ocxr and ocxrs 100 = double compare single-shot mode: initialize ocx pin low, toggle ocx state on matches of ocxr and ocxrs for one cycle 011 = single compare continuous pulse mode: compare events continuously toggle the ocx pin 010 = single compare single-shot mode: initialize ocx pin high, compare event forces the ocx pin low 001 = single compare single-shot mode: initialize ocx pin low, compare event forces the ocx pin high 000 = output compare channel is disabled register 15-1: ocxcon1: output compare x control register 1 (continued) note 1: the comparator module used for fault input varies with the ocx module. oc1 and oc2 use comparator 1; oc3 and oc4 use comparator 2; oc5 uses comparator 3.
? 2011 microchip technology inc. ds39995b-page 163 pic24fv32ka304 family register 15-2: ocxcon2: output compare x control register 2 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 fltmd fltout flttrien ocinv ? dcb1 (3) dcb0 (3) oc32 bit 15 bit 8 r/w-0 r/w-0, hs r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 octrig trigstat octris syncsel4 syncsel3 syncsel2 syncsel1 syncsel0 bit 7 bit 0 legend: hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 fltmd: fault mode select bit 1 = fault mode is maintained until the fault source is removed and the corresponding ocflt0 bit is cleared in software 0 = fault mode is maintained until the fault source is removed and a new pwm period starts bit 14 fltout: fault out bit 1 = pwm output is driven high on a fault 0 = pwm output is driven low on a fault bit 13 flttrien: fault output state select bit 1 = pin is forced to an output on a fault condition 0 = pin i/o condition is unaffected by a fault bit 12 ocinv: ocmp invert bit 1 = ocx output is inverted 0 = ocx output is not inverted bit 11 unimplemented: read as ? 0 ? bit 10-9 dcb<1:0>: oc pulse-width least significant bits (3) 11 = delay ocx falling edge by 3/4 of the instruction cycle 10 = delay ocx falling edge by 1/2 of the instruction cycle 01 = delay ocx falling edge by 1/4 of the instruction cycle 00 = ocx falling edge occurs at start of the instruction cycle bit 8 oc32: cascade two oc modules enable bit (32-bit operation) 1 = cascade module operation is enabled 0 = cascade module operation is disabled bit 7 octrig: ocx trigger/sync select bit 1 = trigger ocx from source designated by syncselx bits 0 = synchronize ocx with source designated by syncselx bits bit 6 trigstat: timer trigger status bit 1 = timer source has been triggered and is running 0 = timer source has not been triggered and is being held clear bit 5 octris: ocx output pin direction select bit 1 = ocx pin is tri-stated 0 = output compare peripheral x is connected to the ocx pin note 1: do not use an oc module as its own trigger source, either by selecting this mode or another equivalent syncsel setting. 2: use these inputs as trigger sources only and never as sync sources. 3: these bits affect the rising edge when ocinv = 1 . the bits have no effect when the ocm bits (ocxcon1<2:0>) = 001 .
pic24fv32ka304 family ds39995b-page 164 ? 2011 microchip technology inc. bit 4-0 syncsel<4:0>: trigger/synchronization source selection bits 11111 = this oc module (1) 11110 = reserved 11101 = reserved 11100 = ctmu (2) 11011 = a/d (2) 11010 = comparator 3 (2) 11001 = comparator 2 (2) 11000 = comparator 1 (2) 10111 = input capture 4 (2) 10110 = input capture 3 (2) 10101 = input capture 2 (2) 10100 = input capture 1 (2) 100xx = reserved 01111 = timer5 01110 = timer4 01101 = timer3 01100 = timer2 01011 = timer1 01010 = input capture 5 (2) 01001 = reserved 01000 = reserved 00111 = reserved 00110 = reserved 00101 = output compare 5 (1) 00100 = output compare 4 (1) 00011 = output compare 3 (1) 00010 = output compare 2 (1) 00001 = output compare 1 (1) 00000 = not synchronized to any other module register 15-2: ocxcon2: output compare x control register 2 (continued) note 1: do not use an oc module as its own trigger source, either by selecting this mode or another equivalent syncsel setting. 2: use these inputs as trigger sources only and never as sync sources. 3: these bits affect the rising edge when ocinv = 1 . the bits have no effect when the ocm bits (ocxcon1<2:0>) = 001 .
? 2011 microchip technology inc. ds39995b-page 165 pic24fv32ka304 family 16.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial data eeproms, shift registers, display drivers, a/d converters, etc. the spi module is compatible with motorola ? spi and siop interfaces. the module supports operation in two buffer modes. in standard mode, data is shifted through a single serial buffer. in enhanced buffer mode, data is shifted through an 8-level fifo buffer. the module also supports a basic framed spi protocol while operating in either master or slave mode. a total of four framed spi configurations are supported. the spi serial interface consists of four pins: ? sdi1: serial data input ? sdo1: serial data output ? sck1: shift clock input or output ? ss1 : active-low slave select or frame synchronization i/o pulse the spi module can be configured to operate using 2, 3 or 4 pins. in the 3-pin mode, ss1 is not used. in the 2-pin mode, both sdo1 and ss1 are not used. block diagrams of the module in standard and enhanced buffer modes are shown in figure 16-1 and figure 16-2 . the devices of the pic24fv32ka304 family offer two spi modules on a device. to set up the spi1 module for the standard master mode of operation: 1. if using interrupts: a) clear the respective spi1if bit in the ifs0 register. b) set the respective spi1ie bit in the iec0 register. c) write the respective spi1ipx bits in the ipc2 register to set the interrupt priority. 2. write the desired settings to the spi1con1 and spi1con2 registers with the msten bit (spi1con1<5>) = 1 . 3. clear the spirov bit (spi1stat<6>). 4. enable spi operation by setting the spien bit (spi1stat<15>). 5. write the data to be transmitted to the spi1buf register. transmission (and reception) will start as soon as data is written to the spi1buf register. to set up the spi module for the standard slave mode of operation: 1. clear the spi1buf register. 2. if using interrupts: a) clear the respective spi1if bit in the ifs0 register. b) set the respective spi1ie bit in the iec0 register. c) write the respective spi1ip bits in the ipc2 register to set the interrupt priority. 3. write the desired settings to the spi1con1 and spi1con2 registers with the msten bit (spi1con1<5>) = 0 . 4. clear the smp bit. 5. if the cke bit is set, then the ssen bit (spi1con1<7>) must be set to enable the ss1 pin. 6. clear the spirov bit (spi1stat<6>). 7. enable spi operation by setting the spien bit (spi1stat<15>). note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the serial peripheral interface, refer to the ?pic24f family reference manual? , section 23. ?serial peripheral interface (spi)? (ds39699). note: do not perform read-modify-write operations (such as bit-oriented instructions) on the spi1buf register in either standard or enhanced buffer mode. note: in this section, the spi modules are referred to as spix. special function registers (sfrs) will follow a similar notation. for example, spi1con1 or spi1con2 refers to the control register for the spi1 module.
pic24fv32ka304 family ds39995b-page 166 ? 2011 microchip technology inc. figure 16-1: spix module block diagram (standard buffer mode) internal data bus sdi1 sdo1 ss1 /fsync1 sck1 spi1sr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler sync spi1buf control transfer transfer write spi1buf read spi1buf 16 spi1con1<1:0> spi1con1<4:2> master clock secondary prescaler 1:1 to 1:8 clock control
? 2011 microchip technology inc. ds39995b-page 167 pic24fv32ka304 family to set up the spi1 module for the enhanced buffer master (ebm) mode of operation: 1. if using interrupts: a) clear the respective spi1if bit in the ifs0 register. b) set the respective spi1ie bit in the iec0 register. c) write the respective spi1ipx bits in the ipc2 register. 2. write the desired settings to the spi1con1 and spi1con2 registers with the msten bit (spi1con1<5>) = 1 . 3. clear the spirov bit (spi1stat<6>). 4. select enhanced buffer mode by setting the spiben bit (spi1con2<0>). 5. enable spi operation by setting the spien bit (spi1stat<15>). 6. write the data to be transmitted to the spi1buf register. transmission (and reception) will start as soon as data is written to the spi1buf register. to set up the spi1 module for the enhanced buffer slave mode of operation: 1. clear the spi1buf register. 2. if using interrupts: a) clear the respective spi1if bit in the ifs0 register. b) set the respective spi1ie bit in the iec0 register. c) write the respective spi1ipx bits in the ipc2 register to set the interrupt priority. 3. write the desired settings to the spi1con1 and spi1con2 registers with the msten bit (spi1con1<5>) = 0 . 4. clear the smp bit. 5. if the cke bit is set, then the ssen bit must be set, thus enabling the ss1 pin. 6. clear the spirov bit (spi1stat<6>). 7. select enhanced buffer mode by setting the spiben bit (spi1con2<0>). 8. enable spi operation by setting the spien bit (spi1stat<15>). figure 16-2: spix module block diagram (enhance d buffer mode) internal data bus sdi1 sdo1 ss1 /fsync1 sck1 spi1sr bit 0 shift control edge select f cy enable sync spi1buf control transfer transfer write spi1buf read spi1buf 16 spi1con1<1:0> spi1con1<4:2> master clock 8-level fifo transmit buffer 8-level fifo receive buffer clock control primary 1:1/4/16/64 prescaler secondary prescaler 1:1 to 1:8
pic24fv32ka304 family ds39995b-page 168 ? 2011 microchip technology inc. register 16-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc spien ?spisidl ? ? spibec2 spibec1 spibec0 bit 15 bit 8 r-0,hsc r/c-0, hs r/w-0, hsc r/w-0 r/w-0 r/w-0 r-0, hsc r-0, hsc srmpt spirov srxmpt sisel2 sisel1 sisel0 spitbf spirbf bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 spien: spi1 enable bit 1 = enables module and configures sck1, sdo1, sdi1 and ss1 as serial port pins 0 = disables module bit 14 unimplemented: read as ? 0 ? bit 13 spisidl: stop in idle mode bit 1 = discontinues module operation when device enters idle mode 0 = continues module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10-8 spibec<2:0>: spi1 buffer element count bits (valid in enhanced buffer mode) master mode: number of spi transfers pending. slave mode: number of spi transfers unread. bit 7 srmpt: shift register (spi1sr) empty bit (valid in enhanced buffer mode) 1 = spi1 shift register is empty and ready to send or receive 0 = spi1 shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new byte/word is completely received and discarded (the user software has not read the previous data in the spi1buf register.) 0 = no overflow has occurred bit 5 srxmpt: receive fifo empty bit (valid in enhanced buffer mode) 1 = receive fifo is empty 0 = receive fifo is not empty bit 4-2 sisel<2:0>: spi1 buffer interrupt mode bits (valid in enhanced buffer mode) 111 = interrupt when spix transmit buffer is full (spitbf bit is set) 110 = interrupt when last bit is shifted into spi1sr; as a result, the tx fifo is empty 101 = interrupt when the last bit is shifted out of spi1sr; now the transmit is complete 100 = interrupt when one data byte is shifted into the spi1sr; as a result, the tx fifo has one open spot 011 = interrupt when spix receive buffer is full (spirbf bit set) 010 = interrupt when spix receive buffer is 3/4 or more full 001 = interrupt when data is available in receive buffer (srmpt bit is set) 000 = interrupt when the last data in the receive buffer is read; as a result, the buffer is empty (srxmpt bit is set)
? 2011 microchip technology inc. ds39995b-page 169 pic24fv32ka304 family bit 1 spitbf: spi1 transmit buffer full status bit 1 = transmit not yet started, spixtxb is full 0 = transmit started, spixtxb is empty in standard buffer mode: automatically set in hardware when cpu writes spixbuf location, loading spixtxb. automatically cleared in hardware when spix module transfers data from spixtxb to spixsr. in enhanced buffer mode: automatically set in hardware when cpu writes spixbuf location, loading the last available buffer location. automatically cleared in hardware when a buffer location is available for a cpu write. bit 0 spirbf: spix receive buffer full status bit 1 = receive is complete, spixrxb is full 0 = receive is not complete, spixrxb is empty in standard buffer mode: automatically set in hardware when spi1 transfers data from spixsr to spixrxb. automatically cleared in hardware when core reads spixbuf location, reading spixrxb. in enhanced buffer mode: automatically set in hardware when spix transfers data from spixsr to buffer, filling the last unread buffer location. automatically cleared in hardware when a buffer location is available for a transfer from spixsr. register 16-1: spixstat: spix status and control register (continued)
pic24fv32ka304 family ds39995b-page 170 ? 2011 microchip technology inc. register 16-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dissck dissdo mode16 smp cke (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ckp msten spre2 spre1 spre0 ppre1 ppre0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 dissck: disable sck1 pin bit (spi master modes only) 1 = internal spi clock is disabled, pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disables sdo1 pin bit 1 = sdo1 pin is not used by module; pin functions as i/o 0 = sdo1 pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spi1 data input sample phase bit master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode: smp must be cleared when spi1 is used in slave mode. bit 8 cke: spi1 clock edge select bit (1) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: slave select enable bit (slave mode) 1 =ss1 pin is used for slave mode 0 =ss1 pin is not used by module; pin controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 =slave mode bit 4-2 spre<2:0>: secondary prescale bits (master mode) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 . . . 000 = secondary prescale 8:1 note 1: the cke bit is not used in the framed spi modes. the user should program this bit to ? 0 ? for the framed spi modes (frmen = 1 ).
? 2011 microchip technology inc. ds39995b-page 171 pic24fv32ka304 family bit 1-0 ppre<1:0>: primary prescale bits (master mode) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 16-2: spi x con1: spix control register 1 (continued) note 1: the cke bit is not used in the framed spi modes. the user should program this bit to ? 0 ? for the framed spi modes (frmen = 1 ). register 16-3: spixcon2: spi1 control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd spifpol ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? spife spiben bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 frmen: framed spi1 support bit 1 = framed spi1 support is enabled 0 = framed spi1 support is disabled bit 14 spifsd: frame sync pulse direction control on ss1 pin bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 spifpol: frame sync pulse polarity bit (frame mode only) 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as ? 0 ? bit 1 spife: frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 spiben: enhanced buffer enable bit 1 = enhanced buffer is enabled 0 = enhanced buffer is disabled (legacy mode)
pic24fv32ka304 family ds39995b-page 172 ? 2011 microchip technology inc. equation 16-1: relationship between device and spi clock speed (1) table 16-1: sample sck frequencies (1,2) f cy = 16 mhz secondary prescaler settings 1:12:14:16:18:1 primary prescaler settings 1:1 invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 f cy = 5 mhz primary prescaler settings 1:1 5000 2500 1250 833 625 4:1 1250 625 313 208 156 16:1 313 156 78 52 39 64:17839201310 note 1: based on f cy = f osc /2; doze mode and pll are disabled. 2: sck1 frequencies indicated in khz. primary prescaler * secondary prescaler f cy f sck = note 1: based on f cy = f osc /2; doze mode and pll are disabled.
? 2011 microchip technology inc. ds39995b-page 173 pic24fv32ka304 family 17.0 inter-integrated circuit? (i 2 c?) the inter-integrated circuit (i 2 c?) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial data eeproms, display drivers, a/d converters, etc. the i 2 c module supports these features: ? independent master and slave logic ? 7-bit and 10-bit device addresses ? general call address, as defined in the i 2 c protocol ? clock stretching to provide delays for the processor to respond to a slave data request ? both 100 khz and 400 khz bus specifications ? configurable address masking ? multi-master modes to prevent loss of messages in arbitration ? bus repeater mode, allowing the acceptance of all messages as a slave, regardless of the address ? automatic scl a block diagram of the module is shown in figure 17-1 . 17.1 pin remapping options the i 2 c module is tied to a fixed pin. to allow flexibility with peripheral multiplexing, the i2c1 module, in 28-pin devices, can be reassigned to the alternate pins. these alternate pins are designated as scl1 and sda1 during device configuration. pin assignment is controlled by the i2c1sel configuration bit. programming this bit (= 0 ) multiplexes the module to the scl1 and sda1 pins. 17.2 communicating as a master in a single master environment the details of sending a message in master mode depends on the communications protocol for the device being communicated with. typically, the sequence of events is as follows: 1. assert a start condition on sda1 and scl1. 2. send the i 2 c device address byte to the slave with a write indication. 3. wait for and verify an acknowledge from the slave. 4. send the first data byte (sometimes known as the command) to the slave. 5. wait for and verify an acknowledge from the slave. 6. send the serial memory address low byte to the slave. 7. repeat steps 4 and 5 until all data bytes are sent. 8. assert a repeated start condition on sda1 and scl1. 9. send the device address byte to the slave with a read indication. 10. wait for and verify an acknowledge from the slave. 11. enable master reception to receive serial memory data. 12. generate an ack or nack condition at the end of a received byte of data. 13. generate a stop condition on sda1 and scl1. note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the inter-integrated circuit, refer to the ?pic24f family reference manual? , section 24. ?inter-integrated circuit? (i 2 c?)? (ds39702).
pic24fv32ka304 family ds39995b-page 174 ? 2011 microchip technology inc. figure 17-1: i 2 c? block diagram i2c1rcv internal data bus scl1 sda1 shift match detect i2c1add start and stop bit detect clock address match clock stretching i2c1trn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2c1con i2c1stat control logic read lsb write read i2c1brg i2c1rsr write read write read write read write read write read i2c1msk
? 2011 microchip technology inc. ds39995b-page 175 pic24fv32ka304 family 17.3 setting baud rate when operating as a bus master to compute the baud rate generator (brg) reload value, use equation 17-1 . equation 17-1: computing baud rate reload value (1) 17.4 slave address masking the i2c1msk register ( register 17-3 ) designates address bit positions as ?don?t care? for both 7-bit and 10-bit addressing modes. setting a particular bit location (= 1 ) in the i2c1msk register causes the slave module to respond, whether the corresponding address bit value is ? 0 ? or ? 1 ?. for example, when i2c1msk is set to ? 00100000 ?, the slave module will detect both addresses: ? 0000000 ? and ? 00100000 ?. to enable address masking, the intelligent peripheral management interface (ipmi) must be disabled by clearing the ipmien bit (i2c1con<11>). table 17-1: i 2 c? clock rates (1) table 17-2: i 2 c? reserved addresses (1) i2c1brg f cy f scl ----------- - f cy 10 000 000 ?? ----------------------------- - ? ?? ?? 1 ? = f scl f cy i2c1brg 1 f cy 10 000 000 ?? ----------------------------- - ++ --------------------------------------------------------------------- - = or note 1: based on f cy = f osc /2; doze mode and pll are disabled. note: as a result of changes in the i 2 c protocol, the addresses in tab l e 1 7- 2 are reserved and will not be acknowledged in slave mode. this includes any address mask settings that include any of these addresses. required system f scl f cy i2c1brg value actual f scl (decimal) (hexadecimal) 100 khz 16 mhz 157 9d 100 khz 100 khz 8 mhz 78 4e 100 khz 100 khz 4 mhz 39 27 99 khz 400 khz 16 mhz 37 25 404 khz 400 khz 8 mhz 18 12 404 khz 400khz 4mhz 9 9 385khz 400khz 2mhz 4 4 385khz 1 mhz 16 mhz 13 d 1.026 mhz 1mhz 8mhz 6 6 1.026mhz 1mhz 4mhz 3 3 0.909mhz note 1: based on f cy = f osc /2, doze mode and pll are disabled. slave address r/w bit description 0000 000 0 general call address (2) 0000 000 1 start byte 0000 001 x cbus address 0000 010 x reserved 0000 011 x reserved 0000 1xx x hs mode master code 1111 1xx x reserved 1111 0xx x 10-bit slave upper byte (3) note 1: the address bits listed here will never cause an address match, independent of the address mask settings. 2: address will be acknowledged only if gcen = 1 . 3: match on this address can only occur on the upper byte in 10-bit addressing mode.
pic24fv32ka304 family ds39995b-page 176 ? 2011 microchip technology inc. register 17-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1 hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen ? i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 i2cen: i2c1 enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module; all i 2 c? pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 i2csidl: stop in idle mode bit 1 = discontinues module operation when device enters an idle mode 0 = continues module operation in idle mode bit 12 sclrel: scl1 release control bit (when operating as i 2 c slave) 1 = releases sclx clock 0 = holds sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software may write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware is clear at beginning of slave transmission. hardware is clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software may only write ? 1 ? to release clock). hardware is clear at beginning of slave transmission. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit 1 = ipmi support mode is enabled; all addresses acknowledged 0 = ipmi support mode is disabled bit 10 a10m: 10-bit slave addressing bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control is disabled 0 = slew rate control is enabled bit 8 smen: smbus input levels bit 1 = enables i/o pin thresholds compliant with the smbus specification 0 = disables the smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enables interrupt when a general call address is received in the i2c1rsr (module is enabled for reception) 0 = general call address is disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with the sclrel bit. 1 = enables software or receive clock stretching 0 = disables software or receive clock stretching
? 2011 microchip technology inc. ds39995b-page 177 pic24fv32ka304 family bit 5 ackdt: acknowledge data bit (when operating as i 2 c master; applicable during master receive) value that will be transmitted when the software initiates an acknowledge sequence. 1 = sends nack during acknowledge 0 = sends ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master; applicable during master receive) 1 = initiates acknowledge sequence on sdax and sclx pins and transmits ackdt data bit; hardware is clear at end of master acknowledge sequence 0 = acknowledge sequence is not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c; hardware is clear at end of eighth bit of master receive data byte 0 = receive sequence is not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiates stop condition on sdax and sclx pins; hardware is clear at end of master stop sequence 0 = stop condition is not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiates repeated start condition on sdax and sclx pins; hardware clear at end of master repeated start sequence 0 = repeated start condition is not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiates start condition on sdax and sclx pins; hardware is clear at end of master start sequence 0 = start condition is not in progress register 17-1: i2cxcon: i2cx control register (continued)
pic24fv32ka304 family ds39995b-page 178 ? 2011 microchip technology inc. register 17-2: i2cxstat: i2cx status register r-0, hsc r-0, hsc u-0 u-0 u-0 r/c-0, hs r-0, hsc r-0, hsc ackstat trstat ? ? ? bcl gcstat add10 bit 15 bit 8 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d/a psr/w rbf tbf bit 7 bit 0 legend: c = clearable bit hs = hardware settable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ackstat: acknowledge status bit 1 = nack was detected last 0 = ack was detected last hardware is set or clear at end of acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master; applicable to master transmit operation.) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware is set at beginning of master transmissi on; hardware is clear at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detected during a master operation 0 = no collision hardware is set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware is set when address matches general call address; hardware is clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware is set at match of 2 nd byte of matched 10-bit address; hardware is clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write to the i2c1trn register failed because the i 2 c module is busy 0 = no collision hardware is set at occurrence of write to i2c1trn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2c1rcv register is still holding the previous byte 0 = no overflow hardware is set at attempt to transfer i2c1rsr to i2c1rcv (cleared by software). bit 5 d/a : data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was the device address hardware is clear at device address match; hardware is set by write to i2c1trn or by reception of slave byte. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware is set or cleared when start, repeated start or stop detected.
? 2011 microchip technology inc. ds39995b-page 179 pic24fv32ka304 family bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware is set or clear when start, repeated start or stop detected. bit 2 r/w : read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware is set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive is complete, i2c1rcv is full 0 = receive is not complete, i2c1rcv is empty hardware is set when i2c1rcv is written with received byte; hardware is clear when software reads i2c1rcv. bit 0 tbf: transmit buffer full status bit 1 = transmit is in progress, i2cxtrn is full 0 = transmit is complete, i2cxtrn is empty hardware is set when software writes to i2c1trn; hardware is clear at completion of data transmission. register 17-2: i2cxstat: i2cx status register (continued)
pic24fv32ka304 family ds39995b-page 180 ? 2011 microchip technology inc. register 17-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? amsk9 amsk8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as ? 0 ? bit 9-0 amsk<9:0>: mask for address bit x select bits 1 = enable masking for bit x of incoming message address; bit match not is required in this position 0 = disable masking for bit x; bit match is required in this position register 17-4: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ? smbusdel2 smbusdel1 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as ? 0 ? bit 5 smbusdel2: smbus sdax input delay select bit 1 = the i2c2 module is configured for a longer smbus input delay (nominal 300 ns delay) 0 = the i2c2 module is configured for a legacy input delay (nominal 150 ns delay) bit 4 smbusdel1: smbus sdax input delay select bit 1 = the i2c1 module is configured for a longer smbus input delay (nominal 300 ns delay) 0 = the i2c1 module is configured for a legacy input delay (nominal 150 ns delay) bit 3-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 181 pic24fv32ka304 family 18.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in this pic24f device family. the uart is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, lin/j2602, rs-232 and rs-485 interfaces. this module also supports a hardware flow control option with the uxcts and uxrts pins, and also includes an irda ? encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission through the uxtx and uxrx pins ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware flow control option with uxcts and uxrts pins ? fully integrated baud rate generator (ibrg) with 16-bit prescaler ? baud rates ranging from 1 mbps to 15 bps at 16 mips ? 4-deep, first-in-first-out (fifo) transmit data buffer ? 4-deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for 9-bit mode with address detect (9 th bit = 1 ) ? transmit and receive interrupts ? loopback mode for diagnostic support ? support for sync and break characters ? supports automatic baud rate detection ?irda ? encoder and decoder logic ? 16x baud clock output for irda support a simplified block diagram of the uart is shown in figure 18-1 . the uart module consists of these important hardware elements: ? baud rate generator ? asynchronous transmitter ? asynchronous receiver figure 18-1: uart simplified block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the universal asynchronous receiver transmitter, refer to the ?pic24f family reference manual? , section 21. ?uart? (ds39708). uxrx irda ? hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts uxbclk baud rate generator
pic24fv32ka304 family ds39995b-page 182 ? 2011 microchip technology inc. 18.1 uart baud rate generator (brg) the uart module includes a dedicated 16-bit baud rate generator (brg). the uxbrg register controls the period of a free-running, 16-bit timer. equation 18-1 provides the formula for computation of the baud rate with brgh = 0 . equation 18-1: uart baud rate with brgh = 0 (1) example 18-1 provides the calculation of the baud rate error for the following conditions: ?f cy = 4 mhz ? desired baud rate = 9600 the maximum baud rate (brgh = 0 ) possible is f cy /16 (for uxbrg = 0 ) and the minimum baud rate possible is f cy /(16 * 65536). equation 18-2 shows the formula for computation of the baud rate with brgh = 1 . equation 18-2: uart baud rate with brgh = 1 (1) the maximum baud rate (brgh = 1 ) possible is f cy /4 (for uxbrg = 0 ) and the minimum baud rate possible is f cy /(4 * 65536). writing a new value to the uxbrg register causes the brg timer to be reset (cleared). this ensures the brg does not wait for a timer overflow before generating the new baud rate. example 18-1: baud rate erro r calculation (brgh = 0 ) (1) note 1: based on f cy = f osc /2; doze mode and pll are disabled. baud rate = f cy 16 ? (uxbrg + 1) f cy 16 ? baud rate uxbrg = ? 1 baud rate = f cy 4 ? (uxbrg + 1) f cy 4 ? baud rate uxbrg = ? 1 note 1: based on f cy = f osc /2; doze mode and pll are disabled. desired baud rate = f cy /(16 (uxbrg + 1)) solving for uxbrg value: uxbrg = ((f cy /desired baud rate)/16) ? 1 uxbrg = ((4000000/9600)/16) ? 1 uxbrg = 25 calculated baud rate = 4000000/(16 (25 + 1)) = 9615 error = (calculated baud rate ? desired baud rate) desired baud rate = (9615 ? 9600)/9600 =0.16% note 1: based on f cy = f osc /2; doze mode and pll are disabled.
? 2011 microchip technology inc. ds39995b-page 183 pic24fv32ka304 family 18.2 transmitting in 8-bit data mode 1. set up the uart: a) write appropriate values for data, parity and stop bits. b) write appropriate baud rate value to the uxbrg register. c) set up transmit and receive interrupt enable and priority bits. 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt two cycles after being set). 4. write data byte to lower byte of uxtxreg word. the value will be immediately transferred to the transmit shift register (tsr), and the serial bit stream will start shifting out with the next rising edge of the baud clock. 5. alternately, the data byte may be transferred while utxen = 0 , and then, the user may set utxen. this will cause the serial bit stream to begin immediately, because the baud clock will start from a cleared state. 6. a transmit interrupt will be generated as per interrupt control bit, utxiselx. 18.3 transmitting in 9-bit data mode 1. set up the uart (as described in section 18.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. 3. set the utxen bit (causes a transmit interrupt, two cycles after being set). 4. write uxtxreg as a 16-bit value only. 5. a word write to uxtxreg triggers the transfer of the 9-bit data to the tsr. the serial bit stream will start shifting out with the first rising edge of the baud clock. 6. a transmit interrupt will be generated as per the setting of control bit, utxiselx. 18.4 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. 1. configure the uart for the desired mode. 2. set utxen and utxbrk ? sets up the break character. 3. load the uxtxreg with a dummy character to initiate transmission (value is ignored). 4. write ?55h? to uxtxreg ? loads the sync character into the transmit fifo. 5. after the break has been sent, the utxbrk bit is reset by hardware. the sync character now transmits. 18.5 receiving in 8-bit or 9-bit data mode 1. set up the uart (as described in section 18.2 ?transmitting in 8-bit data mode? ). 2. enable the uart. 3. a receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, urxiselx. 4. read the oerr bit to determine if an overrun error has occurred. the oerr bit must be reset in software. 5. read uxrxreg. the act of reading the uxrxreg character will move the next character to the top of the receive fifo, including a new set of perr and ferr values. 18.6 operation of uxcts and uxrts control pins uartx clear to send (uxcts ) and request to send (uxrts ) are the two hardware-controlled pins that are associated with the uart module. these two pins allow the uart to operate in simplex and flow control modes. they are implemented to control the transmission and reception between the data terminal equipment (dte). the uen<1:0> bits in the uxmode register configure these pins. 18.7 infrared support the uart module provides two types of infrared uart support: one is the irda clock output to support an external irda encoder and decoder device (legacy module support), and the other is the full implementation of the irda encoder and decoder. as the irda modes require a 16x baud clock, they will only work when the brgh bit (uxmode<3>) is ? 0 ?. 18.7.1 external irda support ? irda clock output to support external irda encoder and decoder devices, the uxbclk pin (same as the uxrts pin) can be configured to generate the 16x baud clock. when uen<1:0> = 11 , the uxbclk pin will output the 16x baud clock if the uart module is enabled; it can be used to support the irda codec chip. 18.7.2 built-in irda encoder and decoder the uart has full implementation of the irda encoder and decoder as part of the uart module. the built-in irda encoder and decoder functionality is enabled using the iren bit (uxmode<12>). when enabled (iren = 1 ), the receive pin (uxrx) acts as the input from the infrared receiver. the transmit pin (uxtx) acts as the output to the infrared transmitter.
pic24fv32ka304 family ds39995b-page 184 ? 2011 microchip technology inc. register 18-1: uxmode: uartx mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 (2) r/w-0 (2) uarten ? usidl iren (1) rtsmd ? uen1 uen0 bit 15 bit 8 r/c-0, hc r/w-0 r/w-0, hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud rxinv brgh pdsel1 pdsel0 stsel bit 7 bit 0 legend: c = clearable bit hc = hardware clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controlled by port latches; uartx power consumption is minimal bit 14 unimplemented: read as ? 0 ? bit 13 usidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit (1) 1 = irda encoder and decoder are enabled 0 = irda encoder and decoder are disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin is in simplex mode 0 =uxrts pin is in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx enable bits (2) 11 = uxtx, uxrx and uxbclk pins are enabled and used; uxcts pin is controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /uxbclk pins are controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx will continue to sample the uxrx pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = no wake-up enabled bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character ? requires reception of a sync field (55h); cleared in hardware upon completion 0 = baud rate measurement is disabled or completed bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? note 1: this feature is is only available for the 16x brg mode (brgh = 0 ). 2: bit availability depends on pin availability.
? 2011 microchip technology inc. ds39995b-page 185 pic24fv32ka304 family bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 18-1: uxmode: uartx mode register (continued) note 1: this feature is is only available for the 16x brg mode (brgh = 0 ). 2: bit availability depends on pin availability.
pic24fv32ka304 family ds39995b-page 186 ? 2011 microchip technology inc. register 18-2: uxsta: uartx status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0, hc r/w-0 r-0, hsc r-1, hsc utxisel1 utxinv utxisel0 ? utxbrk utxen utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1, hsc r-0, hsc r-0, hsc r/c-0, hs r-0, hsc urxisel1 urxisel0 adden ridle perr ferr oerr urxda bit 7 bit 0 legend: hc = hardware clearable bit hs = hardware settable bit c = clearable bit hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register (tsr), and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted out of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to the transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: irda ? encoder transmit polarity inversion bit if iren = 0 : 1 = uxtx idle ? 0 ? 0 = uxtx idle ? 1 ? if iren = 1 : 1 = uxtx idle ? 1 ? 0 = uxtx idle ? 0 ? bit 12 unimplemented: read as ? 0 ? bit 11 utxbrk: transmit break bit 1 = send sync break on next transmission ? start bit, followed by twelve ? 0 ? bits; followed by stop bit; cleared by hardware upon completion 0 = sync break transmission is disabled or completed bit 10 utxen: transmit enable bit 1 = transmit is enabled; uxtx pin is controlled by uartx 0 = transmit is disabled; any pending transmission is aborted and buffer is reset. uxtx pin is controlled by the port register. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty; a transmission is in progress or queued bit 7-6 urxisel<1:0>: receive interrupt mode selection bits 11 = interrupt is set on rsr transfer, making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on rsr transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is received and transferred from the rsr to the receive buffer; receive buffer has one or more characters.
? 2011 microchip technology inc. ds39995b-page 187 pic24fv32ka304 family bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (clear/read-only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed (clearing a previously set oerr bit ( 1 ? 0 transition) will reset the receiver buffer and the rsr to the empty state) bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data; at least one more character can be read 0 = receive buffer is empty register 18-2: uxsta: uartx status and control register (continued)
pic24fv32ka304 family ds39995b-page 188 ? 2011 microchip technology inc. register 18-3: uxtxreg: uartx transmit register u-x u-x u-x u-x u-x u-x u-x w-x ? ? ? ? ? ? ?utx8 bit 15 bit 8 w-x w-x w-x w-x w-x w-x w-x w-x utx7 utx6 utx5 utx4 utx3 utx2 utx1 utx0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 utx8: data of the transmitted character bit (in 9-bit mode) bit 7-0 utx<7:0>: data of the transmitted character bits register 18-4: uxrxreg: uartx receive register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0, hsc ? ? ? ? ? ? ?urx8 bit 15 bit 8 r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc r-0, hsc urx7 urx6 urx5 urx4 urx3 urx2 urx1 urx0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as ? 0 ? bit 8 urx8: data of the received character bit (in 9-bit mode) bit 7-0 urx<7:0>: data of the received character bits
? 2011 microchip technology inc. ds39995b-page 189 pic24fv32ka304 family 19.0 real-time clock and calendar (rtcc) the rtcc provides the user with a real-time clock and calendar (rtcc) function that can be calibrated. key features of the rtcc module are: ? operates in deep sleep mode ? selectable clock source ? provides hours, minutes and seconds using 24-hour format ? visibility of one half second period ? provides calendar ? weekday, date, month and year ? alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year ? alarm repeat with decrementing counter ? alarm with indefinite repeat chime ? year 2000 to 2099 leap year correction ? bcd format for smaller software overhead ? optimized for long term battery operation ? user calibration of the 32.768 khz clock crystal/32k intrc frequency with periodic auto-adjust ? optimized for long term battery operation ? fractional second synchronization ? calibration to within 2.64 seconds error per month ? calibrates up to 260 ppm of crystal error ? ability to periodically wake up external devices without cpu intervention (external power control) ? power control output for external circuit control ? calibration takes effect every 15 seconds ? runs from any one of the following: - external real-time clock of 32.768 khz -i nternal 31.25 khz lprc clock - 50 hz or 60 hz external input 19.1 rtcc source clock the user can select between the sosc crystal oscillator, lprc internal oscillator or an external 50 hz/60 hz power line input as the clock reference for the rtcc module. this gives the user an option to trade off system cost, accuracy and power consumption, based on the overall system needs. figure 19-1: rtcc block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the real-time clock and calendar, refer to the ?pic24f family reference manual? , section 29. ?real-time clock and calendar (rtcc)? (ds39696). rtcc clock domain cpu clock domain rtcc rtcc prescalers rtcc timer comparator alarm registers with masks repeat counter 0.5 sec rtcc interrupt logic alrmval rtcval alcfgrpt rcfgcal alarm event year mthdy wkdyhr minsec almthdy alwdhr alminsec rtcc interrupt rtsecsel<1:0> rtcoe 10 00 01 clock source 1s pin alarm pulse input from sosc/lprc oscillator or external source
pic24fv32ka304 family ds39995b-page 190 ? 2011 microchip technology inc. 19.2 rtcc module registers the rtcc module registers are organized into three categories: ? rtcc control registers ? rtcc value registers ? alarm value registers 19.2.1 register mapping to limit the register interface, the rtcc timer and alarm time registers are accessed through corresponding register pointers. the rtcc value register window (rtcvalh and rtcvall) uses the rtcptr bits (rcfgcal<9:8>) to select the desired timer register pair (see table 19-1 ). by writing the rtcvalh byte, the rtcc pointer value, the rtcptr<1:0> bits decrement by one until they reach ? 00 ?. once they reach ? 00 ?, the minutes and seconds value will be accessible through rtcvalh and rtcvall until the pointer value is manually changed. table 19-1: rtcval register mapping the alarm value register window (alrmvalh and alrmvall) uses the alrmptr bits (alcfgrpt<9:8>) to select the desired alarm register pair (see table 19-2 ). by writing the alrmvalh byte, the alarm pointer value (alrmptr<1:0> bits) decrements by one until they reach ? 00 ?. once they reach ? 00 ?, the alrmmin and alrmsec value will be accessible through alrmvalh and alrmvall until the pointer value is manually changed. table 19-2: alrmval register mapping considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the alrmvalh or alrmvall bytes, the alrmptr<1:0> value will be decremented. the same applies to the rtcvalh or rtcvall bytes with the rtcptr<1:0> being decremented. 19.2.2 write lock in order to perform a write to any of the rtcc timer registers, the rtcwren bit (rtcpwc<13>) must be set (see example 19-1 ). 19.2.3 selecting rtcc clock source there are four reference source clock options that can be selected for the rtcc using the rtccsel<1:0> bits; 00 = secondary oscillator, 01 = lprc, 10 = 50 hz external clock, and 11 = 60 hz external clock. example 19-1: setting the rtcwren bit rtcptr<1:0> rtcc value register window rtcval<15:8> rtcval<7:0> 00 minutes seconds 01 weekday hours 10 month day 11 ? year alrmptr <1:0> alarm value register window alrmval<15:8> alrmval<7:0> 00 alrmmin alrmsec 01 alrmwd alrmhr 10 alrmmnth alrmday 11 pwcstab pwcsamp note: this only applies to read operations and not write operations. note: to avoid accidental writes to the timer, it is recommended that the rtcwren bit (rcfgcal<13>) is kept clear at any other time. for the rtcwren bit to be set, there is only one instruction cycle time window allowed between the 55h/aa sequence and the setting of rtcwren. therefore, it is recommended that code follow the procedure in example 19-1 . asm volatile(?push w7?); asm volatile(?push w8?); asm volatile(?disi #5?); asm volatile(?mov #0x55, w7?); asm volatile(?mov w7, _nvmkey?); asm volatile(?mov #0xaa, w8?); asm volatile(?mov w8, _nvmkey?); asm volatile(?bset _rcfgcal, #13?); //set the rtcwren bit asm volatile(?pop w8?); asm volatile(?pop w7?);
? 2011 microchip technology inc. ds39995b-page 191 pic24fv32ka304 family 19.2.4 rtcc control registers register 19-1: rcfgcal: rtcc calibration and configuration register (1) r/w-0 u-0 r/w-0 r-0, hsc r-0, hsc r/w-0 r/w-0 r/w-0 rtcen (2) ? rtcwren rtcsync halfsec (3) rtcoe rtcptr1 rtcptr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 rtcen: rtcc enable bit (2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 rtcwren: rtcc value registers write enable bit 1 = rtcvalh and rtcvall registers can be written to by the user 0 = rtcvalh and rtcvall registers are locked out from being written to by the user bit 12 rtcsync: rtcc value registers read synchronization bit 1 = rtcvalh, rtcvall and alcfgrpt registers can change while reading due to a rollover ripple resulting in an invalid data read. if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = rtcvalh, rtcvall or alcfgrpt registers can be read without concern over a rollover ripple bit 11 halfsec: half second status bit (3) 1 = second half period of a second 0 = first half period of a second bit 10 rtcoe: rtcc output enable bit 1 = rtcc output is enabled 0 = rtcc output is disabled bit 9-8 rtcptr<1:0>: rtcc value register window pointer bits points to the corresponding rtcc value registers when reading the rtcvalh and rtcvall registers. the rtcptr<1:0> value decrements on every read or write of rtcvalh until it reaches ? 00 ?. rtcval<15:8>: 00 = minutes 01 = weekday 10 = month 11 = reserved rtcval<7:0>: 00 = seconds 01 = hours 10 = day 11 = year note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only; it is cleared to ? 0 ? on a write to the lower half of the minsec register.
pic24fv32ka304 family ds39995b-page 192 ? 2011 microchip technology inc. bit 7-0 cal<7:0>: rtc drift calibration bits 01111111 = maximum positive adjustment; adds 508 rtc clock pulses every one minute . . . 01111111 = minimum positive adjustment; adds 4 rtc clock pulses every one minute 00000000 = no adjustment 11111111 = minimum negative adjustment; subtracts 4 rtc clock pulses every one minute . . . 10000000 = maximum negative adjustment; subtracts 512 rtc clock pulses every one minute register 19-1: rcfgcal: rtcc calibration and configuration register (1) (continued) note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only; it is cleared to ? 0 ? on a write to the lower half of the minsec register.
? 2011 microchip technology inc. ds39995b-page 193 pic24fv32ka304 family register 19-2: rtcpwc: rtcc configuration register 2 (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwcen pwcpol pwccpre pwcspre rtcclk1 (2) rtcclk0 (2) rtcout1 rtcout0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 pwcen: power control enable bit 1 = power control is enabled 0 = power control is disabled bit 14 pwcpol: power control polarity bit 1 = power control output is active-high 0 = power control output is active-low bit 13 pwccpre: power control control/stability prescaler bits 1 = pwc stability window clock is divide-by-2 of source rtcc clock 0 = pwc stability window clock is divide-by-1 of source rtcc clock bit 12 pwcspre: power control sample prescaler bits 1 = pwc sample window clock is divide-by-2 of source rtcc clock 0 = pwc sample window clock is divide-by-1 of source rtcc clock bit 11-10 rtcclk<1:0>: rtcc clock select bits (2) determines the source of the internal rtcc clock, which is used for all rtcc timer operations. 00 = external secondary oscillator (sosc) 01 = internal lprc oscillator 10 = external power line source ? 50 hz 11 = external power line source ? 60 hz bit 9-8 rtcout<1:0>: rtcc output select bits determines the source of the rtcc pin output. 00 = rtcc alarm pulse 01 = rtcc seconds clock 10 = rtcc clock 11 = power control bit 7-0 unimplemented: read as ? 0 ? note 1: the rtcpwc register is only affected by a por. 2: when a new value is written to these register bits, the seconds value register should also be written to properly reset the clock prescalers in the rtcc.
pic24fv32ka304 family ds39995b-page 194 ? 2011 microchip technology inc. register 19-3: alcfgrpt: al arm configuration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen chime amask3 amask2 amask1 amask0 alrmptr1 alrmptr0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt7 arpt6 arpt5 arpt4 arpt3 arpt2 arpt1 arpt0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 alrmen: alarm enable bit 1 = alarm is enabled (cleared automatically after an alarm event whenever arpt<7:0> = 00h and chime = 0 ) 0 = alarm is disabled bit 14 chime: chime enable bit 1 = chime is enabled; arpt<7:0> bits are allowed to roll over from 00h to ffh 0 = chime is disabled; arpt<7:0> bits stop once they reach 00h bit 13-10 amask<3:0>: alarm mask configuration bits 0000 = every half second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29 th , once every 4 years) 101x = reserved ? do not use 11xx = reserved ? do not use bit 9-8 alrmptr<1:0>: alarm value register window pointer bits points to the corresponding alarm value registers when reading the alrmvalh and alrmvall registers. the alrmptr<1:0> value decrements on every read or write of alrmvalh until it reaches ? 00 ?. alrmval<15:8>: 00 = alrmmin 01 = alrmwd 10 = alrmmnth 11 = unimplemented alrmval<7:0>: 00 = alrmsec 01 = alrmhr 10 = alrmday 11 = unimplemented bit 7-0 arpt<7:0>: alarm repeat counter value bits 11111111 = alarm will repeat 255 more times . . . 00000000 = alarm will not repeat the counter decrements on any alarm event; it is prevented from rolling over from 00h to ffh unless chime = 1 .
? 2011 microchip technology inc. ds39995b-page 195 pic24fv32ka304 family 19.2.5 rtcval register mappings register 19-4: year: year value register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x yrten3 yrten2 yrten2 yrten1 yrone3 yrone2 yrone1 yrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7-4 yrten<3:0>: binary coded decimal value of year?s tens digit bits contains a value from 0 to 9. bit 3-0 yrone<3:0>: binary coded decimal value of year?s ones digit bits contains a value from 0 to 9. note 1: a write to the year register is only allowed when rtcwren = 1 . register 19-5: mthdy: month and day value register (1) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit bit contains a value of ? 0 ? or ? 1 ?. bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit bits contains a value from 0 to 9. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
pic24fv32ka304 family ds39995b-page 196 ? 2011 microchip technology inc. register 19-6: wkdyhr: weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 19-7: minsec: minutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit bits contains a value from 0 to 5. bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit bits contains a value from 0 to 9. bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit bits contains a value from 0 to 9.
? 2011 microchip technology inc. ds39995b-page 197 pic24fv32ka304 family 19.2.6 alrmval register mappings register 19-8: almthdy: alarm month and day value register (1) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? mthten0 mthone3 mthone2 mthone1 mthone0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? dayten1 dayten0 dayone3 dayone2 dayone1 dayone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12 mthten0: binary coded decimal value of month?s tens digit bit contains a value of ? 0 ? or ? 1 ?. bit 11-8 mthone<3:0>: binary coded decimal value of month?s ones digit bits contains a value from 0 to 9. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dayten<1:0>: binary coded decimal value of day?s tens digit bits contains a value from 0 to 3. bit 3-0 dayone<3:0>: binary coded decimal value of day?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 . register 19-9: alwdhr: alarm weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x ? ? ? ? ? wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? ? hrten1 hrten0 hrone3 hrone2 hrone1 hrone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as ? 0 ? bit 10-8 wday<2:0>: binary coded decimal value of weekday digit bits contains a value from 0 to 6. bit 7-6 unimplemented: read as ? 0 ? bit 5-4 hrten<1:0>: binary coded decimal value of hour?s tens digit bits contains a value from 0 to 2. bit 3-0 hrone<3:0>: binary coded decimal value of hour?s ones digit bits contains a value from 0 to 9. note 1: a write to this register is only allowed when rtcwren = 1 .
pic24fv32ka304 family ds39995b-page 198 ? 2011 microchip technology inc. register 19-10: alminsec: alarm mi nutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? minten2 minten1 minten0 minone3 minone2 minone1 minone0 bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? secten2 secten1 secten0 secone3 secone2 secone1 secone0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-12 minten<2:0>: binary coded decimal value of minute?s tens digit bits contains a value from 0 to 5. bit 11-8 minone<3:0>: binary coded decimal value of minute?s ones digit bits contains a value from 0 to 9. bit 7 unimplemented: read as ? 0 ? bit 6-4 secten<2:0>: binary coded decimal value of second?s tens digit bits contains a value from 0 to 5. bit 3-0 secone<3:0>: binary coded decimal value of second?s ones digit bits contains a value from 0 to 9.
? 2011 microchip technology inc. ds39995b-page 199 pic24fv32ka304 family register 19-11: rtccswt: contro l/sample window timer register (1) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x pwcstab7 pwcstab6 pwcstab5 pwcstab4 pwcstab3 pwcstab2 pwcstab1 pwcstab0 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x pwcsamp7 pwcsamp6 pwcsamp5 pwcsamp4 pwcsamp3 pwcsamp2 pwcsamp1 pwcsamp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 pwcstab<7:0>: pwm stability window timer bits 11111111 = stability window is 255 t pwcclk clock periods . . . 00000000 = stability window is 0 t pwcclk clock periods the sample window starts when the alarm event triggers. the stability window timer starts counting from every alarm event when pwcen = 1 . bit 7-0 pwcsamp<7:0>: pwm sample window timer bits 11111111 = sample window is always enabled, even when pwcen = 0 11111110 = sample window is 254 t pwcclk clock periods . . . 00000000 = sample window is 0 t pwcclk clock periods the sample window timer starts counting at the end of the stability window when pwcen = 1 . if pwcstab<7:0> = 0 , the sample window timer starts counting from every alarm event when pwcen = 1 . note 1: writes to this register are only allowed when rtcwren = 1 .
pic24fv32ka304 family ds39995b-page 200 ? 2011 microchip technology inc. 19.3 calibration the real-time crystal input can be calibrated using the periodic auto-adjust feature. when properly calibrated, the rtcc can provide an error of less than 3 seconds per month. this is accomplished by finding the number of error clock pulses and storing the value into the lower half of the rcfgcal register. the 8-bit signed value loaded into the lower half of rcfgcal is multiplied by four and will be either added or subtracted from the rtcc timer, once every minute. refer to the steps below for rtcc calibration: 1. using another timer resource on the device, the user must find the error of the 32.768 khz crystal. 2. once the error is known, it must be converted to the number of error clock pulses per minute. 3. a) if the oscillator is faster than ideal (negative result form step 2), the rcfgcal register value must be negative. this causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) if the oscillator is slower than ideal (positive result from step 2), the rcfgcal register value must be positive. this causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. equation 19-1: writes to the lower half of the rcfgcal register should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse, except when seconds = 00, 15, 30 or 45. this is due to the auto-adjust of the rtcc at 15 second intervals. 19.4 alarm ? configurable from half second to one year ? enabled using the alrmen bit (alcfgrpt<15>) ? one time alarm and repeat alarm options are available 19.4.1 configuring the alarm the alarm feature is enabled using the alrmen bit. this bit is cleared when an alarm is issued. writes to alrmval should only take place when alrmen = 0 . as shown in figure 19-2 , the interval selection of the alarm is configured through the amask bits (alcfgrpt<13:10>). these bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. the alarm can also be configured to repeat based on a preconfigured interval. the amount of times this occurs, once the alarm is enabled, is stored in the arpt<7:0> bits (alcfgrpt<7:0>). when the value of the arpt bits equals 00h and the chime bit (alcfgrpt<14>) is cleared, the repeat function is disabled, and only a single alarm will occur. the alarm can be repeated up to 255 times by loading arpt<7:0> with ffh. after each alarm is issued, the value of the arpt bits is decremented by one. once the value has reached 00h, the alarm will be issued one last time, after which, the alrmen bit will be cleared automatically and the alarm will turn off. indefinite repetition of the alarm can occur if the chime bit = 1 . instead of the alarm being disabled when the value of the arpt bits reaches 00h, it rolls over to ffh and continues counting indefinitely while chime is set. 19.4.2 alarm interrupt at every alarm event, an interrupt is generated. in addition, an alarm pulse output is provided that operates at half the frequency of the alarm. this output is completely synchronous to the rtcc clock and can be used as a trigger clock to other peripherals. (ideal frequency ? ? measured frequency) * 60 = clocks per minute ? ideal frequency = 32,768 hz note: it is up to the user to include, in the error value, the initial error of the crystal: drift due to temperature and drift due to crystal aging. note: changing any of the registers, other than the rcfgcal and alcfgrpt registers, and the chime bit while the alarm is enabled (alrmen = 1 ), can result in a false alarm event leading to a false alarm interrupt. to avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (alrmen = 0 ). it is recommended that the alcfgrpt register and chime bit be changed when rtcsync = 0 .
? 2011 microchip technology inc. ds39995b-page 201 pic24fv32ka304 family figure 19-2: alarm mask settings 19.5 power control the rtcc includes a power control feature that allows the device to periodically wake-up an external device, wait for the device to be stable before sampling wake-up events from that device and then shut down the external device. this can be done completely autonomously by the rtcc, without the need to wake from the current low-power mode (sleep, deep sleep, etc.). to enable this feature, the rtcc must be enabled (rtcen = 1 ), the pwcen register bit must be set and the rtcc pin must be driving the pwc control signal (rtcoe = 1 and rtcsecsel<1:0> = 11 ). the polarity of the pwc control signal may be chosen using the pwcp register bit. active-low or active-high may be used with the appropriate external switch to turn on or off the power to one or more external devices. the active-low setting may also be used in conjunction with an open-drain setting on the rtcc pin. this setting is able to drive the gnd pin(s) of the external device directly (with the appropriate external v dd pull-up device), without the need for external switches. finally, the chime bit should be set to enable the pwc periodicity. note 1: annually, except when configured for february 29. s ss mss mm s s hh mm ss dhhmmss dd hh mm s s mm d d h h mm s s day of the week month day hours minutes seconds alarm mask setting (amask<3:0>) 0000 - every half second 0001 - every second 0010 - every 10 seconds 0011 - every minute 0100 - every 10 minutes 0101 - every hour 0110 - every day 0111 - every week 1000 - every month 1001 - every year (1)
pic24fv32ka304 family ds39995b-page 202 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 203 pic24fv32ka304 family 20.0 32-bit programmable cyclic redundancy check (crc) generator the programmable crc generator provides a hardware implemented method of quickly generating checksums for various networking and security applications. it offers the following features: ? user-programmable crc polynomial equation, up to 32 bits ? programmable shift direction (little or big-endian) ? independent data and polynomial lengths ? configurable interrupt output ? data fifo a simplified block diagram of the crc generator is shown in figure 20-1 . a simple version of the crc shift engine is shown in figure 20-2 . figure 20-1: crc block diagram figure 20-2: crc shift engine detail note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information, refer to the ?pic24f family reference manual? , section 41. ?32-bit programmable cyclic redundancy check (crc)? (ds39729). variable fifo (4x32, 8x16 or 16x8) crcdath crcdatl shift buffer crc shift engine crcwdath crcwdatl lendian 1 0 crcisel 1 0 fifo empty event shift complete event set crcif 2 * f cy shift clock crcwdath crcwdatl bit 0 bit 1 bit n (2) x(1) (1) read/write bus shift buffer data bit 2 x(2) (1) x(n) (1) note 1: each xor stage of the shift engine is programmable; see text for details. 2: polynomial length n is determined by ([plen<3:0>] + 1)
pic24fv32ka304 family ds39995b-page 204 ? 2011 microchip technology inc. 20.1 user interface 20.1.1 polynomial interface the crc module can be programmed for crc polynomials of up to the 32nd order, using up to 32 bits. polynomial length, which reflects the highest exponent in the equation, is selected by the plen<4:0> bits (crccon2<4:0>). the crcxorl and crcxorh registers control which exponent terms are included in the equation. setting a particular bit includes that exponent term in the equation. functionally, this includes an xor operation on the corresponding bit in the crc engine. clearing this bit disables the xor. for example, consider two crc polynomials, one a 16-bit equation and the other, a 32-bit equation: to program these polynomials into the crc generator, set the register bits, as shown in table 20-1 . note that the appropriate positions are set to ? 1 ? to indicate that they are used in the equation (for example, x26 and x23). the 0 bit required by the equation is always xored; thus, x0 is a don?t care. for a polynomial of length, n , it is assumed that the n th bit will always be used, regardless of the bit setting. therefore, for a polynomial length of 32, there is no 32nd bit in the crcxor register. 20.1.2 data interface the module incorporates a fifo that works with a variable data width. input data width can be configured to any value between one and 32 bits using the dwidth<4:0> bits (crccon2<12:8>). when the data width is greater than 15, the fifo is four words deep. when the dwidth value is between 15 and 8, the fifo is 8 words deep. when the dwidth value is less than 8, the fifo is 16 words deep. the data for which the crc is to be calculated must first be written into the fifo. even if the data width is less than 8, the smallest data element that can be written into the fifo is one byte. for example, if the dwidth value is five, then the size of the data is dwidth + 1 or six. the data is written as a whole byte; the two unused upper bits are ignored by the module. once data is written into the msb of the crcdat registers (that is, msb as defined by the data width), the value of the vword<4:0> bits (crccon1<12:8>) increments by one. for example, if the dwidth value is 24, the vword bits will increment when bit 7 of crcdath is written. therefore, crcdatl must always be written before crcdath. the crc engine starts shifting data when the crcgo bit is set and the value of vword is greater than zero. each word is copied out of the fifo into a buffer register, which decrements vword. the data is then shifted out of the buffer. the crc engine continues shifting at a rate of two bits per instruction cycle until the vword value reaches zero. this means that for a given data width, it takes half that number of instructions for each word to complete the calculation. for example, it takes 16 cycles to calculate the crc for a single word of 32-bit data. when the vword value reaches the maximum value for the configured value of dwidth (4, 8 or 16), the crcful bit becomes set. when the vword value reaches zero, the crcmpt bit becomes set. the fifo is emptied and the vword<4:0> bits are set to ? 00000 ? whenever crcen is ? 0 ?. at least one instruction cycle must pass, after a write to crcdat, before a read of the vword bits is done. table 20-1: crc setup examples for 16 and 32-bit polynomial x16 + x12 + x5 + 1 and x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 crc control bits bit values 16-bit polynomial 32-bit polynomial plen<4:0> 01111 11111 x<31:16> 0000 0000 0000 000x 0000 0100 1100 0001 x<15:0> 0001 0000 0010 000x 0001 1101 1011 011x
? 2011 microchip technology inc. ds39995b-page 205 pic24fv32ka304 family 20.1.3 data shift direction the lendian bit (crccon1<3>) is used to control the shift direction. by default, the crc will shift data through the engine, msb first. setting lendian (= 1 ) causes the crc to shift data, lsb first. this setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. note that this only changes the direction of the data that is shifted into the engine. the result of the crc calculation will still be a normal crc result, not a reverse crc result. 20.1.4 interrupt operation the module generates an interrupt that is configurable by the user for either of two conditions. if crcisel is ? 0 ?, an interrupt is generated when the vword<4:0> bits make a transition from a value of ? 1 ? to ? 0 ?. if crcisel is ? 1 ?, an interrupt will be generated after the crc operation finishes and the module sets the crcgo bit to ? 0 ?. manually setting crcgo to ? 0 ? will not generate an interrupt. 20.1.5 typical operation to use the module for a typical crc calculation: 1. set the crcen bit to enable the module. 2. configure the module for the desired operation: a) program the desired polynomial using the crcxorl and crcxorh registers, and the plen<4:0> bits b) configure the data width and shift direction using the dwidth and lendian bits c) select the desired interrupt mode using the crcisel bit 3. preload the fifo by writing to the crcdatl and crcdath registers until the crcful bit is set or no data is left. 4. clear old results by writing 00h to crcwdatl and crcwdath. crcwdat can also be left unchanged to resume a previously halted calculation. 5. set the crcgo bit to start calculation. 6. write remaining data into the fifo as space becomes available. 7. when the calculation completes, crcgo is automatically cleared. an interrupt will be generated if crcisel = 1 . 8. read crcwdatl and crcwdath for the result of the calculation. 20.2 registers there are eight registers associated with the module: ? crccon1 ? crccon2 ? crcxorl ? crcxorh ? crcdatl ? crcdath ? crcwdatl ? crcwdath the crccon1 and crccon2 registers ( register 20-1 and register 20-2 ) control the operation of the module, and configure the various settings. the crcxor registers ( register 20-3 and register 20-4 ) select the polynomial terms to be used in the crc equation. the crcdat and crcwdat registers are each register pairs that serve as buffers for the double-word, input data and crc processed output, respectively.
pic24fv32ka304 family ds39995b-page 206 ? 2011 microchip technology inc. register 20-1: crccon1: crc control register 1 r/w-0 u-0 r/w-0 r-0 r-0 r-0 r-0 r-0 crcen ? csidl vword4 vword3 vword2 vword1 vword0 bit 15 bit 8 r-0, hcs r-1, hcs r/w-0 r/w-0, hc r/w-0 u-0 u-0 u-0 crcful crcmpt crcisel crcgo lendian ? ? ? bit 7 bit 0 legend: hc = hardware clearable bit hcs = hardware clearable/settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 crcen : crc enable bit 1 = module is enabled 0 = module is enabled. all state machines, pointers and crcwdat/crcdat are reset; other sfrs are not reset bit 14 unimplemented: read as ? 0 ? bit 13 csidl: crc stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-8 vword<4:0>: pointer value bits indicates the number of valid words in the fifo. has a maximum value of 8 when plen<3:0> > 7, or 16 when plen<3:0> ?? 7. bit 7 crcful : fifo full bit 1 = fifo is full 0 = fifo is not full bit 6 crcmpt: fifo empty bit 1 = fifo is empty 0 = fifo is not empty bit 5 crcisel: crc interrupt selection bit 1 = interrupt on fifo is empty; crc calculation is not complete 0 = interrupt on shift is complete and crcwdat result is ready bit 4 crcgo: start crc bit 1 = start crc serial shifter 0 = crc serial shifter is turned off bit 3 lendian: data shift direction select bit 1 = data word is shifted into the crc, starting with the lsb (little endian) 0 = data word is shifted into the crc, starting with the msb (big endian) bit 2-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 207 pic24fv32ka304 family register 20-2: crccon2: c rc control register 2 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? dwidth4 dwidth3 dwidth2 dwidth1 dwidth0 bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? plen4 plen3 plen2 plen1 plen0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as ? 0 ? bit 12-8 dwidth<4:0>: data width select bits defines the width of the data word (data word width = (dwidth<4:0>) + 1). bit 7-5 unimplemented: read as ? 0 ? bit 4-0 plen<4:0>: polynomial length select bits defines the length of the crc polynomial (polynomial length = (plen<4:0>) + 1). register 20-3: crcxorl: crc xor polynomial register, low byte r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x15 x14 x13 x12 x11 x10 x9 x8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 x7 x6 x5 x4 x3 x2 x1 ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-1 x<15:1>: xor of polynomial term x n enable bits bit 0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 208 ? 2011 microchip technology inc. register 20-4: crcxorh: crc xor polyno mial register, high byte r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x31 x30 x29 x28 x27 x26 x25 x24 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x23 x22 x21 x20 x19 x18 x17 x16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 x<31:16>: xor of polynomial term x n enable bits
? 2011 microchip technology inc. ds39995b-page 209 pic24fv32ka304 family 21.0 high/low-voltage detect (hlvd) the high/low-voltage detect module (hlvd) is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change. an interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. if the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. the hlvd control register (see register 21-1 ) completely controls the operation of the hlvd module. this allows the circuitry to be ?turned off? by the user under software control, which minimizes the current consumption for the device. figure 21-1: high/low-voltage de tect (hlvd) module block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the high/low-voltage detect, refer to the ?pic24f family reference manual? , section 36. ?high-level integration with programmable high/low-voltage detect (hlvd)? (ds39725). set v dd 16-to-1 mux hlvden hlvdl<3:0> hlvdin v dd externally generated trip point hlvdif hlvden internal voltage reference vdir 1.024v typical -
pic24fv32ka304 family ds39995b-page 210 ? 2011 microchip technology inc. register 21-1: hlvdcon: high/low-v oltage detect control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 hlvden ?hlsidl ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 vdir bgvst irvst ? hlvdl3 hlvdl2 hlvdl1 hlvdl0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 hlvden: high/low-voltage detect power enable bit 1 = hlvd is enabled 0 = hlvd is disabled bit 14 unimplemented: read as ? 0 ? bit 13 hlsidl: hlvd stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 vdir: voltage change direction select bit 1 = event occurs when voltage equals or exceeds trip point (hlvdl<3:0>) 0 = event occurs when voltage equals or falls below trip point (hlvdl<3:0>) bit 6 bgvst: band gap voltage stable flag bit 1 = indicates that the band gap voltage is stable 0 = indicates that the band gap voltage is unstable bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the internal reference voltage is stable and the high-voltage detect logic generates the interrupt flag at the specified voltage range 0 = indicates that the internal reference voltage is unstable and the high-voltage detect logic will not generate the interrupt flag at the specified voltage range, and the hlvd interrupt should not be enabled bit 4 unimplemented: read as ? 0 ? bit 3-0 hlvdl<3:0>: high/low-voltage detection limit bits 1111 = external analog input is used (input comes from the hlvdin pin) 1110 = trip point 1 (1) 1101 = trip point 2 (1) 1100 = trip point 3 (1) . . . 0000 = trip point 15 (1) note 1: for the actual trip point, see section 29.0 ?electrical characteristics? .
? 2011 microchip technology inc. ds39995b-page 211 pic24fv32ka304 family 22.0 12-bit a/d converter with threshold detect the pic24f 12-bit a/d converter has the following key features: ? successive approximation register (sar) conversion ? conversion speeds of up to 100 ksps ? up to 32 analog input channels (internal and external) ? multiple internal reference input channels ? external voltage reference input pins ? unipolar differential sample-and-hold (s/h) amplifier ? automated threshold scan and compare operation to pre-evaluate conversion results ? selectable conversion trigger source ? fixed-length (one word per channel), configurable conversion result buffer ? four options for results alignment ? configurable interrupt generation ? operation during cpu sleep and idle modes the 12-bit a/d converter module is an enhanced version of the 10-bit module offered in some pic24 devices. both modules are successive approximation register (sar) converters at their cores, surrounded by a range of hardware features for flexible configuration. this version of the module extends functionality by providing 12-bit resolution, a wider range of automatic sampling options and tighter integration with other analog modules, such as the ctmu and a configurable results buffer. this module also includes a unique threshold detect feature that allows the module itself to make simple decisions based on the conversion results. a simplified block diagram for the module is illustrated in figure 22-1 . note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the 12-bit a/d converter with threshold detect, refer to the ?pic24f family reference manual? , section 51. ?12-bit a/d converter with threshold detect? (ds39739).
pic24fv32ka304 family ds39995b-page 212 ? 2011 microchip technology inc. figure 22-1: 12-bit a/d converter block diagram comparator 12-bit sar conversion logic v ref + dac an14 an15 an8 an9 an4 an5 an6 an7 an0 an1 an2 an3 v ref - sample control s/h av ss av dd adc1buf0: adc1buf17 ad1con1 ad1con2 ad1con3 ad1chs ad1chitl ad1chith control logic data formatting input mux control conversion control pin config. control internal data bus 16 v r + v r - mux a mux b v inh v inl v inh v inh v inl v inl v r + v r - v r select ctmu v bg ad1cssl ad1cssh avss 0.785 * av dd 0.215 * ad1con5 ctmu v bg temp. sensor v dd v dd
? 2011 microchip technology inc. ds39995b-page 213 pic24fv32ka304 family to perform an a/d conversion: 1. configure the a/d module: a) configure port pins as analog inputs and/or select band gap reference inputs (ans<12:10>, ans<5:0>). b) select voltage reference source to match expected range on analog inputs (ad1con2<15:13>). c) select the analog conversion clock to match the desired data rate with the processor clock (ad1con3<7:0>). d) select the appropriate sample/conversion sequence (ad1con1<7:5> and ad1con3<12:8>). e) select how conversion results are presented in the buffer (ad1con1<9:8>). f) select interrupt rate (ad1con2<5:2>). g) turn on a/d module (ad1con1<15>). 2. configure a/d interrupt (if required): a) clear the ad1if bit. b) select a/d interrupt priority. to perform an a/d sample and conversion using threshold detect scanning: 1. configure the a/d module: a) configure port pins as analog inputs (ans<12:10>, ans<5,0>). b) select voltage reference source to match expected range on analog inputs (ad1con2<15:13>). c) select the analog conversion clock to match the desired data rate with the processor clock (ad1con3<7:0>). d) select the appropriate sample/conversion sequence (ad1con1<7:5>, ad1con3<12:8>). e) select how the conversion results are presented in the buffer (ad1con1<9:8>). f) select interrupt rate (ad1con2<5:2>). 2. configure the threshold compare channels: a) enable auto-scan (asen bit (ad1con<15>)). b) select the compare mode ?greater than, less than or windowed? (cm bits (ad1con5<1:0>)). c) select the threshold compare channels to be scanned (adcssh, adcssl). d) if the ctmu is required as a current source for a threshold compare channel, enable the corresponding ctmu channel (adcctmuenh, adcctmuenl). e) write the threshold values into the corresponding adc1bufn registers. f) turn on the a/d module (ad1con1<15>). 3. configure a/d interrupt (optional): a) clear the ad1if bit. b) select a/d interrupt priority. note: if performing an a/d sample and conversion using threshold detect in sleep mode, the rc a/d clock source must be selected before entering into sleep mode.
pic24fv32ka304 family ds39995b-page 214 ? 2011 microchip technology inc. 22.1 a/d control registers the 12-bit a/d converter module uses up to 43 registers for its operation. all registers are mapped in the data memory space. 22.1.1 control registers depending on the specific device, the module has up to eleven control and status registers: ? ad1con1: a/d control register 1 ? ad1con2: a/d control register 2 ? ad1con3: a/d control register 3 ? ad1con5: a/d control register 5 ? ad1chs: a/d sample select register ? ad1chith and ad1chitl: a/d scan compare hit registers ? ad1cssl and ad1cssh: a/d input scan select registers ? ad1ctmenh and ad1ctmenl: ctmu enable registers the ad1con1, ad1con2 and ad1con3 registers ( register 22-1 , register 22-2 and register 22-3 ) control the overall operation of the a/d module. this includes enabling the module, configuring the conversion clock and voltage reference sources, selecting the sampling and conversion triggers, and manually controlling the sample/convert sequences. the ad1con5 register ( register 22-4 ) specifically controls features of the threshold detect operation, including its function in power-saving modes. the ad1chs register ( register 22-5 ) selects the input channels to be connected to the s/h amplifier. it also allows the choice of input multiplexers and the selection of a reference source for differential sampling. the ad1chith and ad1chitl registers ( register 22-6 and register 22-7 ) are semaphore registers used with threshold detect operations. the status of individual bits, or bit pairs in some cases, indicate if a match condition has occurred. ad1chitl is always implemented, whereas ad1chith may not be implemented in devices with 16 or fewer channels. the ad1cssh/l registers ( register 22-8 and register 22-9 ) select the channels to be included for sequential scanning. the ad1ctmenh/l registers ( register 22-10 and register 22-11 ) select the channel(s) to be used by the ctmu during conversions. selecting a particular channel allows the a/d converter to control the ctmu (particularly, its current source) and read its data through that channel. ad1ctmenl is always implemented, whereas ad1ctmenh may not be implemented in devices with 16 or fewer channels. 22.1.2 a/d result buffers the module incorporates a multi-word, dual port ram, called adc1buf. the buffer is composed of at least the same number of word locations as there are external analog channels for a particular device, with a maximum number of 32. the number of buffer addresses is always even. each of the locations is mapped into the data memory space and is separately addressable. the buffer locations are referred to as adc1buf0 through adc1bufn (up to 31). the a/d result buffers are both readable and writable. when the module is active (ad1con<15> = 1 ), the buffers are read-only, and store the results of a/d conversions. when the module is inactive (ad1con<15> = 0 ), the buffers are both readable and writable. in this state, writing to a buffer location programs a conversion threshold for threshold detect operations. buffer contents are not cleared when the module is deactivated with the adon bit (ad1con1<15>). conversion results and any programmed threshold values are maintained when adon is set or cleared.
? 2011 microchip technology inc. ds39995b-page 215 pic24fv32ka304 family register 22-1: ad1con1: a/d control register 1 r/w-0 u-0 r/w-0 u-0 u-0 r-0 r/w-0 r/w-0 adon ?adsidl ? ? ?form1form0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 hsc r/c-0 hsc ssrc3 ssrc2 ssrc1 ssrc0 ? asam samp done bit 7 bit 0 legend: u = unimplemented bit, read as ?0? c = clearable bit r = reserved bit r = readable bit w = writable bit hsc = hardware settable/clearable bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adon: a/d operating mode bit 1 = a/d converter module is operating 0 = a/d converter is off bit 14 unimplemented: read as ? 0 ? bit 13 adsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10 reserved: maintain as ? 1 ? bit 9-8 form<1:0>: data output format bits (see formats following) 11 = fractional result, signed, left-justified 10 = absolute fractional result, unsigned, left-justified 01 = decimal result, signed, right-justified 00 = absolute decimal result, unsigned, right-justified bit 7-4 ssrc<3:0>: sample clock source select bits 1111 = not available; do not use ?? ?? ? 1000 = not available; do not use 0111 = internal counter ends sampling and starts conversion (auto-convert) 0110 = not available; do not use 0101 = timer1 event ends sampling and starts conversion 0100 = ctmu event ends sampling and starts conversion 0011 = timer5 event ends sampling and starts conversion 0010 = timer3 event ends sampling and starts conversion 0001 = int0 event ends sampling and starts conversion 0000 = clearing the samp bit in software ends sampling and begins conversion bit 3 unimplemented: read as ? 0 ? bit 2 asam: a/d sample auto-start bit 1 = sampling begins immediately after last conversion; samp bit is auto-set 0 = sampling begins when samp bit is manually set bit 1 samp: a/d sample enable bit 1 = a/d sample-and-hold amplifiers are sampling 0 = a/d sample-and-hold are holding bit 0 done: a/d conversion status bit 1 = a/d conversion cycle is completed 0 = a/d conversion cycle is not started or in progress
pic24fv32ka304 family ds39995b-page 216 ? 2011 microchip technology inc. register 22-2: ad1con2: a/d control register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 pvcfg1 pvcfg0 nvcfg0 offcal bufregen cscna ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs (1) smpi4 smpi3 smpi2 smpi1 smpi0 bufm (1) alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 pvcfg<1:0>: converter positive voltage reference configuration bits 11 = internal vrh2 10 = internal vrh1 01 =external v ref + 00 =av dd bit 13 nvcfg0: converter negative voltage reference configuration bits 1 =external v ref - 0 =av ss bit 12 offcal: offset calibration mode select bit 1 = inverting and non-inverting inputs of channel sample-and-hold are connected to av ss 0 = inverting and non-inverting inputs of channel sample-and-hold are connected to normal inputs bit 11 bufregen: a/d buffer register enable bit 1 = conversion result is loaded into buffer location determined by the converted channel 0 = a/d result buffer is treated as a fifo bit 10 cscna: scan input selections for ch0+ during sample a bit 1 = scan inputs 0 = do not scan inputs bit 9-8 unimplemented: read as ? 0 ? bit 7 bufs: buffer fill status bit (1) 1 = a/d is filling the upper half of the buffer; user should access data in the lower half 0 = a/d is filling the lower half of the buffer; user should access data in the upper half bit 6-2 smpi<4:0>: interrupt sample rate select bits 11111 = interrupts at the completion of conversion for each 32nd sample 11110 = interrupts at the completion of conversion for each 31st sample ?? ?? ?? 00001 = interrupts at the completion of conversion for every other sample 00000 = interrupts at the completion of conversion for each sample bit 1 bufm: buffer fill mode select bit (1) 1 = starts buffer filling at ad1buf0 on first interrupt and ad1buf(n/2) on next interrupt (split buffer mode) 0 = starts filling buffer at address, adcbuf0, and each sequential address on successive interrupts (fifo mode) bit 0 alts: alternate input sample mode select bit 1 = uses channel input selects for sample a on first sample and sample b on next sample 0 = always uses channel input selects for sample a note 1: only applicable when the buffer is used in fifo mode (bufregen = 0 ). in addition, bufs is only used when bufm = 1 .
? 2011 microchip technology inc. ds39995b-page 217 pic24fv32ka304 family register 22-3: ad1con3: a/d control register 3 r/w-0 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc extsam ? samc4 samc3 samc2 samc1 samc0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs7 adcs6 adcs5 adcs4 adcs3 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 adrc: a/d conversion clock source bit 1 = rc clock 0 = clock derived from system clock bit 14 extsam: extended sampling time bit 1 = a/d is still sampling after samp = 0 0 = a/d is finished sampling bit 13 reserved: maintain as ? 0 ? bit 12-8 samc<4:0>: auto-sample time select bits 11111 = 31 t ad ?? ?? ?? 00001 =1 t ad 00000 =0 t ad bit 7-0 adcs<7:0>: a/d conversion clock select bits 11111111 - 01000000 = reserved 00111111 = 64 t cy =t ad ?? ?? ?? 00000001 = 2 t cy =t ad 00000000 = t cy =t ad
pic24fv32ka304 family ds39995b-page 218 ? 2011 microchip technology inc. register 22-4: ad1con5: a/d control register 5 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 asen lpen ctmreq bgreq vrsreq ? asint1 asint0 bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? wm1 wm0 cm1 cm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 asen: auto-scan enable bit 1 = auto-scan is enabled 0 = auto-scan is disabled bit 14 lpen: low-power enable bit 1 = return to low-power mode after scan 0 = remain in full-power mode after scan bit 13 ctmreq: ctmu request bit 1 = ctmu is enabled when the adc is enabled and active 0 = ctmu is not enabled by the adc bit 12 bgreq: band gap request bit 1 = band gap is enabled when the adc is enabled and active 0 = band gap is not enabled by the adc bit 11 vrsreq: vreg scan request bit 1 = on-chip regulator is enabled when the adc is enabled and active 0 = on-chip regulator is not enabled by the adc bit 10 unimplemented: read as ? 0 ? bit 9-8 asint<1:0>: auto-scan (threshold detect) interrupt mode bits 11 = interrupt after threshold detect sequence completed and valid compare has occurred 10 = interrupt after valid compare has occurred 01 = interrupt after threshold detect sequence completed 00 = no interrupt bit 7-4 unimplemented: read as ? 0 ? bit 3-2 wm<1:0>: write mode bits 11 = reserved 10 = auto-compare only (conversion results are not saved, but interrupts are generated when a valid match, as defined by cm and asint bits, occurs) 01 = convert and save (conversion results are saved to locations as determined by register bits when a match, as defined by cm bits, occurs) 00 = legacy operation (conversion data saved to location determined by buffer register bits) bit 1-0 cm<1:0>: compare mode bits 11 = outside window mode (valid match occurs if the conversion result is outside of the window defined by the corresponding buffer pair) 10 = inside window mode (valid match occurs if the conv ersion result is inside the window defined by the corresponding buffer pair) 01 = greater than mode (valid match occurs if the result is greater than value in the corresponding buffer register) 00 = less than mode (valid match occurs if the result is less than value in the corresponding buffer register)
? 2011 microchip technology inc. ds39995b-page 219 pic24fv32ka304 family register 22-5: ad1chs: a/d sample select register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb2 ch0nb1 ch0nb0 ch0sb4 ch0sb3 ch0sb2 ch0sb1 ch0sb0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na2 ch0na1 ch0na0 ch0sa4 ch0sa3 ch0sa2 ch0sa1 ch0sa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-13 ch0nb<2:0>: sample b channel 0 negative input select bits 111 = an6 (1) 110 = an5 (2) 101 = an4 100 = an3 011 = an2 010 = an1 001 = an0 000 = av ss bit 12-8 ch0sb<4:0>: s/h amplifier positive input select for mux b multiplexer setting bits 11111 = unimplemented, do not use 11101 = av dd (3) 11101 = av ss (3) 11100 = upper guardband rail (0.785 * v dd ) 11011 = lower guardband rail (0.215 * v dd ) 11010 = internal band gap reference (v bg ) (3) 11001 - 10010 = unimplemented, do not use 10001 = no channels connected, all inputs floating (used for ctmu) 10000 = no channels connected, all inputs floating (used for ctmu temperature sensor input) 01111 = an15 01110 = an14 01101 = an13 01100 = an12 01011 = an11 01010 = an10 01001 = an9 01000 = an8 (1) 00111 = an7 (1) 00110 = an6 (1) 00101 = an5 (2) 00100 = an4 00011 = an3 00010 = an2 00001 = an1 00000 = an0 bit 7-5 ch0na<2:0>: sample a channel 0 negative input select bits same definitions as for chonb<2:0>. bit 4-0 ch0sa<4:0>: sample a channel 0 positive input select bits same definitions as for chona<4:0>. note 1: implemented on 44-pin devices only. 2: implemented on 28-pin and 44-pin devices only. 3: actual band gap value used for this input is selected by the pvcfg bits (ad1con2<15:14>).
pic24fv32ka304 family ds39995b-page 220 ? 2011 microchip technology inc. register 22-6: ad1chith: a/d scan compare hit register (high word) (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? chh17 chh16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ?. bit 1-0 chh<17:16>: a/d compare hit bits if cm<1:0> = 11 : 1 = a/d result buffer x has been written with data or a match has occurred 0 = a/d result buffer x has not been written with data for all other values of cm<1:0>: 1 = a match has occurred on a/d result channel x 0 =no match has occurred on a/d result channel x note 1: unimplemented channels are read as ? 0 ?. register 22-7: ad1chitl: a/d scan compare hit register (low word) (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chh15 chh14 chh13 chh12 chh11 chh10 chh9 chh8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chh7 chh6 chh5 chh4 chh3 chh2 chh1 chh0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 chh<15:0>: a/d compare hit bits if cm<1:0> = 11 : 1 = a/d result buffer x has been written with data or a match has occurred 0 = a/d result buffer x has not been written with data for all other values of cm<1:0>: 1 = a match has occurred on a/d result channel n 0 = no match has occurred on a/d result channel n note 1: unimplemented channels are read as ? 0 ?.
? 2011 microchip technology inc. ds39995b-page 221 pic24fv32ka304 family register 22-8: ad1cssh: a/d input scan select register (high word) (1) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 ? css30 css29 css28 css27 css26 ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? css17 css16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14-10 css<30:26>: a/d input scan selection bits 1 = include corresponding channel for input scan 0 = skip channel for input scan bit 9-2 unimplemented: read as ? 0 ? bit 1-0 css<17:16>: a/d input scan selection bits 1 = include corresponding channel for input scan 0 = skip channel for input scan note 1: unimplemented channels are read as ? 0 ?. do not select unimplemented channels for sampling as indeterminate results may be produced. register 22-9: ad1cssl: a/d input scan select register (low word) (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css15 css14 css13 css12 css11 css10 css9 css8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css7 css6 css5 css4 css3 css2 css1 css0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 css<15:0>: a/d input scan selection bits 1 = include corresponding anx input for scan 0 = skip channel for input scan note 1: unimplemented channels are read as ? 0 ?. do not select unimplemented channels for sampling as indeterminate results may be produced.
pic24fv32ka304 family ds39995b-page 222 ? 2011 microchip technology inc. register 22-10: ad1ctmenh: ctmu enable register (high word) (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? ctmen17 ctmen16 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as ? 0 ?. bit 1-0 ctmen<17:16>: ctmu enabled during conversion bits 1 = ctmu is enabled and connected to the selected channel during conversion 0 =ctmu is not connected to this channel note 1: unimplemented channels are read as ? 0 ?. register 22-11: ad1ctmenl: ctmu enable register (low word) (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ctmen15 ctmen14 ctmen13 ctmen12 ctmuen11 ctmen10 ctmen9 ctmen8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ctmen7 ctmen6 ctmen5 ctmen4 ctmen3 ctmen2 ctmen1 ctmen0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-0 ctmen<15:0>: ctmu enabled during conversion bits 1 = ctmu is enabled and connected to the selected channel during conversion 0 = ctmu is not connected to this channel note 1: unimplemented channels are read as ? 0 ?.
? 2011 microchip technology inc. ds39995b-page 223 pic24fv32ka304 family 22.2 a/d sampling requirements the analog input model of the 12-bit a/d converter is shown in figure 22-2 . the total sampling time for the a/d is a function of the holding capacitor charge time. for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the voltage level on the analog input pin. the source impedance (r s ), the interconnect impedance (r ic ) and the internal sampling switch (r ss ) impedance combine to directly affect the time required to charge c hold . the combined impedance of the analog sources must, therefore, be small enough to fully charge the holding capacitor within the chosen sample time. to minimize the effects of pin leakage currents on the accuracy of the a/d converter, the maximum recommended source impedance, r s , is 2.5 k ? . after the analog input channel is selected (changed), this sampling function must be completed prior to starting the conversion. the internal holding capacitor will be in a discharged state prior to each sample operation. at least 1 t ad time period should be allowed between conversions for the sample time. for more details, see section 29.0 ?electrical characteristics? . equation 22-1: a/d conversion clock period figure 22-2: 12-bit a/d converter analog input model t ad t cy adcs 1 + ?? adcs t ad t cy --------- - 1 ? = = note: based on t cy = 2/f osc ; doze mode and pll are disabled. c pin va rs anx i leakage r ic ? 250 ? sampling switch r ss c hold v ss = 4.4 pf ? 500 na legend: c pin v t i leakage r ic r ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch resistance = sample-and-hold capacitance (from dac) various junctions note: c pin value depends on device package and is not tested. effect of c pin negligible if rs ? 5 k ? . r ss ? 3 k ?
pic24fv32ka304 family ds39995b-page 224 ? 2011 microchip technology inc. 22.3 transfer function the transfer functions of the a/d converter in 12-bit resolution are shown in figure 22-3 . the difference of the input voltages, (v inh ? v inl ), is compared to the reference, ((v r +) ? (v r -)). ? the first code transition occurs when the input voltage is ((v r +) ? (v r -))/4096 or 1.0 lsb. ?the 0000 0000 0001 code is centered at v r - + (1.5 * ((v r +) ? (v r -))/4096). ?the 0010 0000 0000 code is centered at v refl + (2048.5 * ((v r +) ? (v r -))/4096). ? an input voltage less than v r - + (((v r -) ? (v r -))/4096) converts as 0000 0000 0000 . ? an input voltage greater than (v r -) + (1023 ((v r +) ? (v r -))/4096) converts as 1111 1111 1111 . figure 22-3: 12-bit a/ d transfer function 0010 0000 0001 (2049) 0010 0000 0010 (2050) 0010 0000 0011 (2051) 0001 1111 1101 (2045) 0001 1111 1110 (2046) 0001 1111 1111 (2047) 1111 1111 1110 (4094) 1111 1111 1111 (4095) 0000 0000 0000 (0) 0000 0000 0001 (1) output code 0010 0000 0000 (2048) (v inh ? v inl ) v r- v r+ ? v r- 4096 2048 * (v r+ ? v r- ) 4096 v r+ v r- + v r- + 4095 * (v r+ ? v r- ) 4096 v r- + 0 (binary (decimal)) voltage level
? 2011 microchip technology inc. ds39995b-page 225 pic24fv32ka304 family 23.0 comparator module the comparator module provides three dual input comparators. the inputs to the comparator can be configured to use any one of four external analog inputs, as well as a voltage reference input from either the internal band gap reference, divided by 2 (v bg /2), or the comparator voltage reference generator. the comparator outputs may be directly connected to the cxout pins. when the respective coe equals ? 1 ?, the i/o pad logic makes the unsynchronized output of the comparator available on the pin. a simplified block diagram of the module is shown in figure 23-1 . diagrams of the possible individual comparator configurations are shown in figure 23-2 . each comparator has its own control register, cmxcon ( register 23-1 ), for enabling and configuring its operation. the output and event status of all three comparators is provided in the cmstat register ( register 23-2 ). figure 23-1: comparator module block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the comparator module, refer to the ?pic24f family reference manual? , section 46. ?scalable comparator module? (ds39734). c1 v in - v in + c x inb c x inc c x ina c x ind cv ref v bg /2 c3 v in - v in + coe c1out pin cpol trigger/interrupt logic cevt evpol<1:0> cout input select logic cch<1:0> cref coe c3out pin cpol trigger/interrupt logic cevt evpol<1:0> cout c2 v in - v in + coe c2out pin cpol trigger/interrupt logic cevt cout
pic24fv32ka304 family ds39995b-page 226 ? 2011 microchip technology inc. figure 23-2: individual comparator configurations cx v in - v in + off (read as ? 0 ?) comparator off con = 0 , cref = x , cch<1:0> = xx comparator cxinb > cxina compare con = 1 , cref = 0 , cch<1:0> = 00 coe cxout cx v in - v in + coe c x inb c x ina comparator cxind > cxina compare con = 1 , cref = 0 , cch<1:0> = 10 cx v in - v in + coe cxout c x ind c x ina comparator cxinc > cxina compare con = 1 , cref = 0 , cch<1:0> = 01 cx v in - v in + coe c x inc c x ina comparator v bg > cxina compare con = 1 , cref = 0 , cch<1:0> = 11 cx v in - v in + coe v bg /2 c x ina comparator cxinb > cv ref compare con = 1 , cref = 1 , cch<1:0> = 00 cx v in - v in + coe c x inb cv ref comparator cxind > cv ref compare con = 1 , cref = 1 , cch<1:0> = 10 cx v in - v in + coe c x ind cv ref comparator cxinc > cv ref compare con = 1 , cref = 1 , cch<1:0> = 01 cx v in - v in + coe c x inc cv ref comparator v bg > cv ref compare con = 1 , cref = 1 , cch<1:0> = 11 cx v in - v in + coe v bg /2 cv ref pin pin cxout pin cxout pin cxout pin cxout pin cxout pin cxout pin cxout pin - - - - -- - - -
? 2011 microchip technology inc. ds39995b-page 227 pic24fv32ka304 family register 23-1: cmxcon: comp arator x control registers r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r-0 con coe cpol clpwr ? ? cevt cout bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 evpol1 evpol0 ? cref ? ? cch1 cch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 con: comparator enable bit 1 = comparator is enabled 0 = comparator is disabled bit 14 coe: comparator output enable bit 1 = comparator output is present on the cxout pin 0 = comparator output is internal only bit 13 cpol: comparator output polarity select bit 1 = comparator output is inverted 0 = comparator output is not inverted bit 12 clpwr: comparator low-power mode select bit 1 = comparator operates in low-power mode 0 = comparator does not operate in low-power mode bit 11-10 unimplemented: read as ? 0 ? bit 9 cevt: comparator event bit 1 = comparator event defined by evpol<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = comparator event has not occurred bit 8 cout: comparator output bit when cpol = 0 : 1 =v in + > v in - 0 =v in + < v in - when cpol = 1 : 1 =v in + < v in - 0 =v in + > v in - bit 7-6 evpol<1:0>: trigger/event/interrupt polarity select bits 11 = trigger/event/interrupt generated on any change of the comparator output (while cevt = 0 ) 10 = trigger/event/interrupt generated on transition of the comparator output: if cpol = 0 (non-inverted polarity): high-to-low transition only. if cpol = 1 (inverted polarity): low-to-high transition only. 01 = trigger/event/interrupt generated on transition of comparator output if cpol = 0 (non-inverted polarity): low-to-high transition only. if cpol = 1 (inverted polarity): high-to-low transition only. 00 = trigger/event/interrupt generation is disabled bit 5 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 228 ? 2011 microchip technology inc. bit 4 cref: comparator reference select bits (non-inverting input) 1 = non-inverting input connects to internal cv ref voltage 0 = non-inverting input connects to cxina pin bit 3-2 unimplemented: read as ? 0 ? bit 1-0 cch<1:0>: comparator channel select bits 11 = inverting input of comparator connects to v bg /2 10 = inverting input of comparator connects to cxind pin 01 = inverting input of comparator connects to cxinc pin 00 = inverting input of comparator connects to cxinb pin register 23-1: cmxcon: comparator x control registers (continued) register 23-2: cmstat: comparat or module status register r/w-0 u-0 u-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc cmidl ? ? ? ? c3evt c2evt c1evt bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r-0, hsc r-0, hsc r-0, hsc ? ? ? ? ? c3out c2out c1out bit 7 bit 0 legend: hsc = hardware settable/clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 cmidl: comparator stop in idle mode bit 1 = discontinue operation of all comparators when device enters idle mode 0 = continue operation of all enabled comparators in idle mode bit 14-11 unimplemented: read as ? 0 ? bit 10 c3evt: comparator 3 event status bit (read-only) shows the current event status of comparator 2 (cm3con<9>). bit 9 c2evt: comparator 2 event status bit (read-only) shows the current event status of comparator 2 (cm2con<9>). bit 8 c1evt: comparator 1 event status bit (read-only) shows the current event status of comparator 1 (cm1con<9>). bit 7-3 unimplemented: read as ? 0 ? bit 2 c3out: comparator 3 output status bit (read-only) shows the current output of comparator 3 (cm3con<8>). bit 1 c2out: comparator 2 output status bit (read-only) shows the current output of comparator 2 (cm2con<8>). bit 0 c1out: comparator 1 output status bit (read-only) shows the current output of comparator 1 (cm1con<8>).
? 2011 microchip technology inc. ds39995b-page 229 pic24fv32ka304 family 24.0 comparator voltage reference 24.1 configuring the comparator voltage reference the comparator voltage reference module is controlled through the cvrcon register ( register 24-1 ). the comparator voltage reference provides a range of output voltages, with 32 distinct levels. the comparator voltage reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref -. the voltage source is selected by the cvrss bit (cvrcon<5>). the settling time of the comparator voltage reference must be considered when changing the cv ref output. figure 24-1: comparator volt age reference block diagram note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the comparator voltage reference, refer to the ?pic24f family reference manual? , section 20. ?comparator module voltage reference module? (ds39709). 32-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 32 steps cv ref av ss
pic24fv32ka304 family ds39995b-page 230 ? 2011 microchip technology inc. register 24-1: cvrcon: comparator vo ltage reference control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrss cvr4 cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as ? 0 ? bit 7 cvren: comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe: comparator v ref output enable bit 1 =cv ref voltage level is output on cv ref pin 0 =cv ref voltage level is disconnected from cv ref pin bit 5 cvrss: comparator v ref source selection bit 1 = comparator reference source, cv rsrc = v ref + ? v ref - 0 = comparator reference source, cv rsrc = av dd ? av ss bit 4-0 cvr<4:0>: comparator v ref value selection 0 cvr<4:0> 31 bits when cv rss = 1 : cv ref = (v ref -) + (cvr<4:0>/32) ? (v ref + ? v ref -) w hen cv rss = 0 : cv ref = (av ss ) + (cvr<4:0>/32) ? (av dd ? av ss )
? 2011 microchip technology inc. ds39995b-page 231 pic24fv32ka304 family 25.0 charge time measurement unit (ctmu) the charge time measurement unit (ctmu) is a flexible analog module that provides charge measurement, accurate differential time measurement between pulse sources and asynchronous pulse generation. its key features include: ? thirteen external edge input trigger sources ? polarity control for each edge source ? control of edge sequence ? control of response to edge levels or edge transitions ? time measurement resolution of one nanosecond ? accurate current source suitable for capacitive measurement together with other on-chip analog modules, the ctmu can be used to precisely measure time, measure capacitance, measure relative changes in capacitance, or generate output pulses that are independent of the system clock. the ctmu module is ideal for interfacing with capacitive-based touch sensors. the ctmu is controlled through three registers: ctmucon1, ctmucon2 and ctmuicon. ctmucon1 enables the module and controls the mode of operation of the ctmu, as well as controlling edge sequencing. ctmucon2 controls edge source selec- tion and edge source polarity selection. the ctmuicon register selects the current range of current source and trims the current. 25.1 measuring capacitance the ctmu module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. the pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (oc1 and timer1) and up to 13 external pins (cted1 through cted13). this pulse is used with the module?s precision current source to calculate capacitance according to the relationship: equation 25-1: for capacitance measurements, the a/d converter samples an external capacitor (c app ) on one of its input channels after the ctmu output?s pulse. a precision resistor (r pr ) provides current source calibration on a second a/d channel. after the pulse ends, the converter determines the voltage on the capacitor. the actual calculation of capacitance is performed in software by the application. figure 25-1 illustrates the external connections used for capacitance measurements, and how the ctmu and a/d modules are related in this application. this example also shows the edge events coming from timer1, but other configurations using external edge sources are possible. a detailed discussion on measuring capacitance and time with the ctmu module is provided in the ? pic24f family reference manual? . note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the charge measurement unit, refer to the ?pic24f family reference manual? , section 53. ?charge time measurement unit (ctmu) with threshold detect? (ds39743). ic dv dt ------ - ? =
pic24fv32ka304 family ds39995b-page 232 ? 2011 microchip technology inc. figure 25-1: typical connections and internal configuration for capacitance measurement pic24f device a/d converter ctmu anx c app output pulse edg1 edg2 r pr an y timer1 current source
? 2011 microchip technology inc. ds39995b-page 233 pic24fv32ka304 family 25.2 measuring time time measurements on the pulse width can be similarly performed using the a/d module?s internal capacitor (c ad ) and a precision resistor for current calibration. figure 25-2 displays the external connections used for time measurements, and how the ctmu and a/d modules are related in this application. this example also shows both edge events coming from the external cted pins, but other configurations using internal edge sources are possible. 25.3 pulse generation and delay the ctmu module can also generate an output pulse with edges that are not synchronous with the device?s system clock. more specifically, it can generate a pulse with a programmable delay from an edge event input to the module. when the module is configured for pulse generation delay by setting the tgen bit (ctmucon<12>), the internal current source is connected to the b input of comparator 2. a capacitor (c delay ) is connected to the comparator 2 pin, c2inb, and the comparator voltage reference, cv ref , is connected to c2ina. cv ref is then configured for a specific trip point. the module begins to charge c delay when an edge event is detected. when c delay charges above the cv ref trip point, a pulse is output on ctpls. the length of the pulse delay is determined by the value of c delay and the cv ref trip point. figure 25-3 illustrates the external connections for pulse generation, as well as the relationship of the different analog modules required. while cted1 is shown as the input pulse source, other options are available. a detailed discussion on pulse generation with the ctmu module is provided in the ? pic24f family reference manual? . figure 25-2: typical co nnections and internal configuration for time measurement figure 25-3: typical co nnections and internal co nfiguration for pulse delay generation pic24f device a/d converter ctmu cted x cted x anx output pulse edg1 edg2 c ad r pr current source c2 cv ref ctpls pic24f device current source comparator ctmu cted x c2inb c delay edg1 -
pic24fv32ka304 family ds39995b-page 234 ? 2011 microchip technology inc. register 25-1: ctmucon1: ct mu control register 1 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ctmuen ? ctmusidl tgen edgen edgseqen idissen cttrig bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 ctmuen: ctmu enable bit 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 ctmusidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 tgen: time generation enable bit 1 = enables edge delay generation 0 = disables edge delay generation bit 11 edgen: edge enable bit 1 = edges are not blocked 0 = edges are blocked bit 10 edgseqen: edge sequence enable bit 1 = edge 1 event must occur before edge 2 event can occur 0 = no edge sequence is needed bit 9 idissen: analog current source control bit 1 = analog current source output is grounded 0 = analog current source output is not grounded bit 8 cttrig: trigger control bit 1 = trigger output is enabled 0 = trigger output is disabled bit 7-0 unimplemented: read as ? 0 ?
? 2011 microchip technology inc. ds39995b-page 235 pic24fv32ka304 family register 25-2: ctmucon2: ct mu control register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 edg1edge edg1pol edg1sel3 edg1sel 2 edg1sel1 edg1sel0 edg2 edg1 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 edg2edge edg2pol edg2sel3 e dg2sel2 edg2sel1 edg2sel0 ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 edg1edge: edge 1 edge-sensitive select bit 1 = input is edge-sensitive 0 = input is level-sensitive bit 14 edg1pol: edge 1 polarity select bit 1 = edge 1 is programmed for a positive edge response 0 = edge 1 is programmed for a negative edge response bit 13-10 edg1sel<3:0>: edge 1 source select bits 1111 = edge 1 source is comparator 3 output 1110 = edge 1 source is comparator 2 output 1101 = edge 1 source is comparator 1 output 1100 = edge 1 source is ic3 1011 = edge 1 source is ic2 1010 = edge 1 source is ic1 1001 = edge 1 source is cted8 1000 = edge 1 source is cted7 0111 = edge 1 source is cted6 0110 = edge 1 source is cted5 0101 = edge 1 source is cted4 0100 = edge 1 source is cted3 (2) 0011 = edge 1 source is cted1 0010 = edge 1 source is cted2 0001 = edge 1 source is oc1 0000 = edge 1 source is timer1 bit 9 edg2: edge 2 status bit indicates the status of edge 2 and can be written to control current source. 1 = edge 2 has occurred 0 = edge 2 has not occurred bit 8 edg1: edge 1 status bit indicates the status of edge 1 and can be written to control current source. 1 = edge 1 has occurred 0 = edge 1 has not occurred bit 7 edg2edge: edge 2 edge-sensitive select bit 1 = input is edge-sensitive 0 = input is level-sensitive note 1: edge sources, cted11 and cted12, are not available on pic24fv32ka302 devices. 2: edge sources, cted3,cted11, cted12 and cted13, are not available on pic24fv32ka301 devices.
pic24fv32ka304 family ds39995b-page 236 ? 2011 microchip technology inc. bit 6 edg2pol: edge 2 polarity select bit 1 = edge 2 is programmed for a positive edge 0 = edge 2 is programmed for a negative edge bit 5-2 edg2sel<3:0>: edge 2 source select bits 1111 = edge 2 source is comparator 3 output 1110 = edge 2 source is comparator 2 output 1101 = edge 2 source is comparator 1 output 1100 = unimplemented; do not use 1011 = edge 2 source is ic3 1010 = edge 2 source is ic2 1001 = edge 2 source is ic1 1000 = edge 2 source is cted13 (2) 0111 = edge 2 source is cted12 (1,2) 0110 = edge 2 source is cted11 (1,2) 0101 = edge 2 source is cted10 0100 = edge 2 source is cted9 0011 = edge 2 source is cted1 0010 = edge 2 source is cted2 0001 = edge 2 source is oc1 0000 = edge 2 source is timer1 bit 1-0 unimplemented: read as ? 0 ? register 25-2: ctmucon2: ctmu control register 2 (continued) note 1: edge sources, cted11 and cted12, are not available on pic24fv32ka302 devices. 2: edge sources, cted3,cted11, cted12 and cted13, are not available on pic24fv32ka301 devices.
? 2011 microchip technology inc. ds39995b-page 237 pic24fv32ka304 family register 25-3: ctmuicon: ctmu current control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 itrim5 itrim4 itrim3 itrim2 itrim1 itrim0 irng1 irng0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 itrim<5:0>: current source trim bits 011111 = maximum positive change from nominal current 011110 . . . 000001 = minimum positive change from nominal current 000000 = nominal current output specified by irng<1:0> 111111 = minimum negative change from nominal current . . . 100010 100001 = maximum negative change from nominal current bit 9-8 irng<1:0>: current source range select bits 11 = 100 x base current 10 = 10 base current 01 = base current level (0.55 a nominal) 00 = 1000 x base current bit 7-0 unimplemented: read as ? 0 ?
pic24fv32ka304 family ds39995b-page 238 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 239 pic24fv32ka304 family 26.0 special features pic24fv32ka304 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: ? flexible configuration ? watchdog timer (wdt) ? code protection ? in-circuit serial programming? (icsp?) ? in-circuit emulation 26.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location, f80000h. a complete list is provided in table 26-1 . a detailed explanation of the various bit functions is provided in register 26-1 through register 26-8 . the address, f80000h, is beyond the user program memory space. in fact, it belongs to the configuration memory space (800000h-ffffffh), which can only be accessed using table reads and table writes. table 26-1: configuration registers locations register 26-1: fbs: boot se gment configuration register note: this data sheet summarizes the features of this group of pic24f devices. it is not intended to be a comprehensive reference source. for more information on the watchdog timer, high-level device integration and programming diagnostics, refer to the individual sec- tions of the ?pic24f family reference manual? provided below: ? section 9. ?watchdog timer (wdt)? (ds39697) ? section 36. ?high-level integration with programmable high/low- voltage detect (hlvd)? (ds39725) ? section 33. ?programming and diagnostics? (ds39716) configuration register address fbs f80000 fgs f80004 foscsel f80006 fosc f80008 fwdt f8000a fpor f8000c ficd f8000e fds f80010 u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? bss2 bss1 bss0 bwrp bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3-1 bss<2:0>: boot segment program flash code protection bits 111 = no boot program flash segment 011 = reserved 110 = standard security, boot program flash segment starts at 200h, ends at 000afeh 010 = high-security boot program flash segment starts at 200h, ends at 000afeh 101 = standard security, boot program flash segment starts at 200h, ends at 0015feh (1) 001 = high-security, boot program flash segment starts at 200h, ends at 0015feh (1) 100 = standard security; boot program flash segment starts at 200h, ends at 002bfeh (1) 000 = high-security; boot program flash segment starts at 200h, ends at 002bfeh (1) bit 0 bwrp: boot segment program flash write protection bit 1 = boot segment may be written 0 = boot segment is write-protected note 1: this selection should not be used in pic24fv16ka3xx devices.
pic24fv32ka304 family ds39995b-page 240 ? 2011 microchip technology inc. register 26-2: fgs: general se gment configuration register register 26-3: foscsel: oscillator selection configuration register u-0 u-0 u-0 u-0 u-0 u-0 r/c-1 r/c-1 ? ? ? ? ? ? gss0 gwrp bit 7 bit 0 legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ? bit 1 gss0: general segment code flash code protection bit 1 = no protection 0 = standard security is enabled bit 0 gwrp: general segment code flash write protection bit 1 = general segment may be written 0 = general segment is write-protected r/p-1 r/p-1 r/p-1 u-0 u-0 r/p-1 r/p-1 r/p-1 ieso lprcsel soscsrc ? ? fnosc2 fnosc1 fnosc0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ieso: internal external switchover bit 1 = internal external switchover mode is enabled (two-speed start-up is enabled) 0 = internal external switchover mode is disabled (two-speed start-up is disabled) bit 6 lprcsel: internal lprc oscillator power select bit 1 = high-power/high-accuracy mode 0 = low-power/low-accuracy mode bit 5 soscsrc: secondary oscillator clock source configuration bit 1 = sosc analog crystal function is available on the sosci/sosco pins 0 = sosc crystal is disabled; digital sclki function is selected on sosco pin bit 4-3 unimplemented: read as ? 0 ? bit 2-0 fnosc<2:0>: oscillator selection bits 000 = fast rc oscillator (frc) 001 = fast rc oscillator with divide-by-n with pll module (frcdiv+pll) 010 = primary oscillator (xt, hs, ec) 011 = primary oscillator with pll module (hs+pll, ec+pll) 100 = secondary oscillator (sosc) 101 = low-power rc oscillator (lprc) 110 = 500 khz low-power frc oscillator with divide-by-n (lpfrcdiv) 111 = 8 mhz frc oscillator with divide-by-n (frcdiv)
? 2011 microchip technology inc. ds39995b-page 241 pic24fv32ka304 family register 26-4: fosc: oscilla tor configuration register r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 fcksm1 fcksm0 soscsel poscfreq1 poscfreq0 osciofnc poscmd1 poscmd0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 fcksm<1:0>: clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled bit 5 soscsel: secondary oscillator power selection configuration bit 1 = secondary oscillator is configured for high-power operation 0 = secondary oscillator is configured for low-power operation bit 4-3 poscfreq<1:0>: primary oscillator frequency range configuration bits 11 = primary oscillator/external clock input frequency is greater than 8 mhz 10 = primary oscillator/external clock input frequency is between 100 khz and 8 mhz 01 = primary oscillator/external clock input frequency is less than 100 khz 00 = reserved; do not use bit 2 osciofnc: clko enable configuration bit 1 = clko output signal active on the osco pin; primary oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmd<1:0> = 11 or 00 ) 0 = clko output disabled bit 1-0 poscmd<1:0>: primary oscillator configuration bits 11 = primary oscillator mode is disabled 10 = hs oscillator mode is selected 01 = xt oscillator mode is selected 00 = external clock mode is selected
pic24fv32ka304 family ds39995b-page 242 ? 2011 microchip technology inc. register 26-5: fwdt: watchdog timer configuration register r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 fwdten1 windis fwdten0 fwpsa wdtps3 wdtps2 wdtps1 wdtps0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7,5 fwdten<1:0>: watchdog timer enable bit 11 = wdt is enabled in hardware 10 = wdt is controlled with the swdten bit setting 01 = wdt is enabled only while device is active; wdt is disabled in sleep; swdten bit is disabled 00 = wdt is disabled in hardware; swdten bit is disabled bit 6 windis: windowed watchdog timer disable bit 1 = standard wdt is selected; windowed wdt is disabled 0 = windowed wdt is enabled; note that executing a clrwdt instruction while the wdt is disabled in hardware and software (fwdten<1:0> = 00 and rcon bit, swdten = 0 ) will not cause a device reset bit 4 fwpsa: wdt prescaler bit 1 = wdt prescaler ratio of 1:128 0 = wdt prescaler ratio of 1:32 bit 3-0 wdtps<3:0>: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1
? 2011 microchip technology inc. ds39995b-page 243 pic24fv32ka304 family register 26-6: fpor: rese t configuration register r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 mclre (2) borv1 (3) borv0 (3) i2c1sel (1) pwrten lvrcfg (1) boren1 boren0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 mclre: mclr pin enable bit (2) 1 = mclr pin is enabled; ra5 input pin is disabled 0 = ra5 input pin is enabled; mclr is disabled bit 6-5 borv<1:0>: brown-out reset enable bits (3) 11 = brown-out reset set to lowest voltage 10 = brown-out reset 01 = brown-out reset set to highest voltage 00 = downside protection on por is enabled ? ?zero-power? is selected bit 4 i2c1sel: alternate i2c1 pin mapping bit (1) 1 = default location for scl1/sda1 pins 0 = alternate location for scl1/sda1 pins bit 3 pwrten: power-up timer enable bit 1 = pwrt is enabled 0 = pwrt is disabled bit 2 lvrcfg: low-voltage regulator configuration bit (1) 1 = low-voltage regulator is not available 0 = low-voltage regulator is available and controlled by the lvren bit (rcon<12>) during sleep bit 1-0 boren<1:0>: brown-out reset enable bits 11 = brown-out reset is enabled in hardware; sboren bit is disabled 10 = brown-out reset is enabled only while device is active and disabled in sleep; sboren bit is disabled 01 = brown-out reset is controlled with the sboren bit setting 00 = brown-out reset is disabled in hardware; sboren bit is disabled note 1: this setting only applies to the ?fv? devices. this bit is reserved and should be maintained as ? 1 ? on ?f? devices. 2: the mclre fuse can only be changed when using the v pp -based icsp? mode entry. this prevents a user from accidentally locking out the device from the low-voltage test entry. 3: refer to section 29.0 ?electrical characteristics? for bor voltages.
pic24fv32ka304 family ds39995b-page 244 ? 2011 microchip technology inc. register 26-7: ficd: in-circuit debugger configuration register r/p-1 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 debug ? ? ? ? ? ficd1 ficd0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 debug : background debugger enable bit 1 = background debugger is disabled 0 = background debugger functions are enabled bit 6-2 unimplemented: read as ? 0 ? bit 1-0 ficd<1:0:> icd pin select bits 11 = pgec1/pged1 are used for programming and debugging the device 10 = pgec2/pged2 are used for programming and debugging the device 01 = pgec3/pged3 are used for programming and debugging the device 00 = reserved; do not use
? 2011 microchip technology inc. ds39995b-page 245 pic24fv32ka304 family register 26-8: fds: deep sleep configuration register r/p-1 r/p-1 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 dswdten dsboren ? dswdtosc dswdtps3 dswdtps2 dswdtps1 dswdtps0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 dswdten: deep sleep watchdog timer enable bit 1 = dswdt is enabled 0 = dswdt is disabled bit 6 dsboren: deep sleep/low-power bor enable bit (does not affect operation in non deep sleep modes) 1 = deep sleep bor is enabled in deep sleep 0 = deep sleep bor is disabled in deep sleep bit 5 unimplemented: read as ? 0 ? bit 4 dswdtosc: dswdt reference clock select bit 1 = dswdt uses lprc as reference clock 0 = dswdt uses sosc as reference clock bit 3-0 dswdtps<3:0>: deep sleep watchdog timer postscale select bits the dswdt prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) nominal 1110 = 1:536,870,912 (6.4 days) nominal 1101 = 1:134,217,728 (38.5 hours) nominal 1100 = 1:33,554,432 (9.6 hours) nominal 1011 = 1:8,388,608 (2.4 hours) nominal 1010 = 1:2,097,152 (36 minutes) nominal 1001 = 1:524,288 (9 minutes) nominal 1000 = 1:131,072 (135 seconds) nominal 0111 = 1:32,768 (34 seconds) nominal 0110 = 1:8,192 (8.5 seconds) nominal 0101 = 1:2,048 (2.1 seconds) nominal 0100 = 1:512 (528 ms) nominal 0011 = 1:128 (132 ms) nominal 0010 = 1:32 (33 ms) nominal 0001 = 1:8 (8.3 ms) nominal 0000 = 1:2 (2.1 ms) nominal
pic24fv32ka304 family ds39995b-page 246 ? 2011 microchip technology inc. register 26-9: devid: device id register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 rrrrrrrr famid7 famid6 famid5 famid4 famid3 famid2 famid1 famid0 bit 15 bit 8 rrrrrrrr dev7 dev6 dev5 dev4 dev3 dev2 dev1 dev0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-16 unimplemented: read as ? 0 ? bit 15-8 famid<7:0>: device family identifier bits 01000101 = pic24fv32ka304 family bit 7-0 dev<7:0>: individual device identifier bits 00010111 = pic24fv32ka304 00000111 = pic24fv16ka304 00010011 = pic24fv32ka302 00000011 = pic24fv16ka302 00011001 = pic24fv32ka301 00001001 = pic24fv16ka301 00010110 = pic24f32ka304 00000110 = pic24f16ka304 00010010 = pic24f32ka302 00000010 = pic24f16ka302 00011000 = pic24f32ka301 00001000 = pic24f16ka301
? 2011 microchip technology inc. ds39995b-page 247 pic24fv32ka304 family register 26-10: devrev: device revision register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 23 bit 16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 r r r r ? ? ? ? rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 23-4 unimplemented: read as ? 0 ? bit 3-0 rev<3:0>: minor revision identifier bits
pic24fv32ka304 family ds39995b-page 248 ? 2011 microchip technology inc. 26.2 on-chip voltage regulator all of the pic24fv32ka304 family of devices power their core digital logic at a nominal 3.0v. this may create an issue for designs that are required to operate at a higher typical voltage, as high as 5.0v. to simplify system design, all devices in the ??fv?? family incorpo- rate an on-chip regulator that allows the device to run its core logic from v dd . the regulator is always enabled and provides power to the core from the other v dd pins. a low-esr capacitor (such as ceramic) must be connected to the v cap pin ( figure 26-1 ). this helps to maintain the stability of the regulator. the recommended value for the filter capac- itor is provided in section 29.1 ?dc characteristics? . in all of the pic24fj64ga family of devices, the regulator is disabled. for the ??f?? devices, the v ddcore and v dd pins are internally tied together to operate at an overall lower allowable voltage range (1.8-3.6v). refer to figure 26-1 for possible configurations. 26.2.1 voltage regulator tracking mode and low-voltage detection for all pic24fv32ka304 devices, the on-chip regula- tor provides a constant voltage of 3.0v nominal to the digital core logic. the regulator can provide this level from a v dd of about 3.0v, all the way up to the device?s v ddmax . it does not have the capability to boost v dd levels below 3.0v. in order to prevent ?brown out? con- ditions when the voltage drops too low for the regulator, the regulator enters tracking mode. in tracking mode, the regulator output follows v dd with a typical voltage drop of 100 mv. when the device enters tracking mode, it is no longer possible to operate at full speed. to provide information about when the device enters tracking mode, the on-chip regulator includes a simple, high/low-voltage detect (hlvd) circuit. when v dd drops below full-speed operating voltage, the circuit sets the high/low-voltage detect interrupt flag, hlvdif (ifs4<8>). this can be used to generate an interrupt and put the application into a low-power operational mode or trigger an orderly shutdown. high/low-voltage detection is only available for ??fv?? parts. figure 26-1: conne ctions for the on-chip regulator 26.2.2 on-chip regulator and por for pic24fv32ka304 devices, it takes approximately 1 ? s for it to generate output. during this time, desig- nated as tpm, code execution is disabled. tpm is applied every time the device resumes operation after any power-down, including sleep mode. 26.3 watchdog timer (wdt) for the pic24fv32ka304 family of devices, the wdt is driven by the lprc oscillator. when the wdt is enabled, the clock source is also enabled. the nominal wdt clock source from lprc is 31 khz. this feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the fwpsa configuration bit. with a 31 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the configuration bits, wdtps<3:0> (fwdt<3:0>), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. using the prescaler and postscaler time-out periods, ranging from 1 ms to 131 seconds, can be achieved. v dd v cap v ss pic24fv32ka304 c efc 5.0v (10 ? f typ) regulator enabled: note 1: these are typical operating voltages. refer to section 29.0 ?electrical characteristics? for the full operating ranges of v dd and v ddcore .
? 2011 microchip technology inc. ds39995b-page 249 pic24fv32ka304 family the wdt, prescaler and postscaler are reset: ? on any device reset ? on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc bits) or by hardware (i.e., fail-safe clock monitor) ? when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) ? when the device exits sleep or idle mode to resume normal operation ?by a clrwdt instruction during normal execution if the wdt is enabled in hardware (fwdten<1:0> = 11 ), it will continue to run during sleep or idle modes. when the wdt time-out occurs, the device will wake and code execution will continue from where the pwrsav instruction was executed. the corresponding sleep or idle bits (rcon<3:2>) will need to be cleared in software after the device wakes up. the wdt flag bit, wdto (rcon<4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. 26.3.1 windowed operation the watchdog timer has an optional fixed window mode of operation. in this windowed mode, clrwdt instructions can only reset the wdt during the last 1/4 of the programmed wdt period. a clrwdt instruction executed before that window causes a wdt reset, similar to a wdt time-out. windowed wdt mode is enabled by programming the configuration bit, windis (fwdt<6>), to ? 0 ?. 26.3.2 control register the wdt is enabled or disabled by the fwdten<1:0> configuration bits. when both the fwdten<1:0> con- figuration bits are set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten<1:0> configuration bits have been pro- grammed to ? 10 ?. the wdt is enabled in software by setting the swdten control bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user to enable the wdt for critical code segments, and disable the wdt during non-critical segments, for maximum power sav- ings. when the fwten<1:0> bits are set to ? 01 ?, the wdt is enabled only in run and idle modes, and is dis- abled in sleep. software control of the wdt swdten bit (rcon<5>) is disabled with this setting. figure 26-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. lprc input wdt overflow wake from sleep 31 khz prescaler postscaler fwpsa swdten fwdten reset all device resets sleep or idle mode lprc control clrwdt instr. pwrsav instr. (5-bit/7-bit) 1:1 to 1:32.768 wdtps<3:0> 1 ms/4 ms exit sleep or idle mode wdt counter transition to new clock source
pic24fv32ka304 family ds39995b-page 250 ? 2011 microchip technology inc. 26.4 deep sleep watchdog timer (dswdt) in pic24fv32ka304 family devices, in addition to the wdt module, a dswdt module is present which runs while the device is in deep sleep, if enabled. it is driven by either the sosc or lprc oscillator. the clock source is selected by the configuration bit, dswcksel (fds<4>). the dswdt can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler. the postscaler can be selected by the configuration bits, dswdtps<3:0> (fds<3:0>). when the dswdt is enabled, the clock source is also enabled. dswdt is one of the sources that can wake-up the device from deep sleep mode. 26.5 program verification and code protection for all devices in the pic24fv32ka304 family, code protection for the boot segment is controlled by the configuration bit, bss0, and the general segment by the configuration bit, gss0. these bits inhibit external reads and writes to the program memory space this has no direct effect in normal execution mode. write protection is controlled by bit, bwrp, for the boot segment and bit, gwrp, for the general segment in the configuration word. when these bits are programmed to ? 0 ?, internal write and erase operations to program memory are blocked. 26.6 in-circuit serial programming pic24fv32ka304 family microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock (pgecx) and data (pgedx) and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 26.7 in-circuit debugger when mplab ? icd 3, mplab real ice? or pickit? 3 is selected as a debugger, the in-circuit debugging functionality is enabled. this function allows simple debugging functions when used with mplab ide. debugging functionality is controlled through the pgecx and pgedx pins. to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss , pgecx, pgedx and the pin pair. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins.
? 2011 microchip technology inc. ds39995b-page 251 pic24fv32ka304 family 27.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 27.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic24fv32ka304 family ds39995b-page 252 ? 2011 microchip technology inc. 27.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 27.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 27.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 27.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2011 microchip technology inc. ds39995b-page 253 pic24fv32ka304 family 27.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 27.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 27.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip?s most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 27.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer?s pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic24fv32ka304 family ds39995b-page 254 ? 2011 microchip technology inc. 27.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 27.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 27.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits.
? 2011 microchip technology inc. ds39995b-page 255 pic24fv32ka304 family 28.0 instruction set summary the pic24f instruction set adds many enhancements to the previous pic ? mcu instruction sets, while maintaining an easy migration from previous pic mcu instruction sets. most instructions are a single program memory word. only three instructions require two program memory locations. each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? word or byte-oriented operations ? bit-oriented operations ? literal operations ? control operations table 28-1 lists the general symbols used in describing the instructions. the pic24f instruction set summary in tab l e 2 8- 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriented w register instructions (including barrel shift instructions) have three operands: ? the first source operand, which is typically a register ?wb? without any address modifier ? the second source operand, which is typically a register ?ws? with or without an address modifier ? the destination of the result, which is typically a register ?wd? with or without an address modifier however, word or byte-oriented file register instructions have two operands: ? the file register specified by the value, ?f? ? the destination, which could either be the file register, ?f?, or the w0 register, which is denoted as ?wreg? most bit-oriented instructions (including simple rotate/shift instructions) have two operands: ? the w register (with or without an address modifier) or file register (specified by the value of ?ws? or ?f?) ? the bit in the w register or file register (specified by a literal value or indirectly by the contents of register ?wb?) the literal instructions that involve data movement may use some of the following operands: ? a literal value to be loaded into a w register or file register (specified by the value of ?k?) ? the w register or file register where the literal value is to be loaded (specified by ?wb? or ?f?) however, literal instructions that involve arithmetic or logical operations use some of the following operands: ? the first source operand, which is a register ?wb? without any address modifier ? the second source operand, which is a literal value ? the destination of the result (only if not the same as the first source operand), which is typically a register ?wd? with or without an address modifier the control instructions may use some of the following operands: ? a program memory address ? the mode of the table read and table write instructions all instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all of the required information is available in these 48 bits. in the second word, the 8 msbs are ? 0 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter (pc) is changed as a result of the instruction. in these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (unconditional/computed branch), indirect call/goto , all table reads and writes, and return/retfie instructions, which are single-word instructions but take two or three cycles. certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. the double-word instructions execute in two instruction cycles. note: this chapter is a brief summary of the pic24f instruction set architecture and is not intended to be a comprehensive reference source.
pic24fv32ka304 family ds39995b-page 256 ? 2011 microchip technology inc. table 28-1: symbols used in opcode descriptions field description #text means literal defined by ? text ? (text) means ?content of text ? [text] means ?the location addressed by text ? { } optional field or operation register bit field .b byte mode selection .d double-word mode selection .s shadow register select .w word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) ?? {0...15} c, dc, n, ov, z mcu status bits: carry, digit carry, negative, overflow, sticky zero expr absolute address, label or expression (resolved by the linker) f file register address ?? {0000h...1fffh} lit1 1-bit unsigned literal ?? {0,1} lit4 4-bit unsigned literal ?? {0...15} lit5 5-bit unsigned literal ?? {0...31} lit8 8-bit unsigned literal ?? {0...255} lit10 10-bit unsigned literal ?? {0...255} for byte mode, {0:1023} for word mode lit14 14-bit unsigned literal ?? {0...16384} lit16 16-bit unsigned literal ?? {0...65535} lit23 23-bit unsigned literal ?? {0...8388608}; lsb must be ? 0 ? none field does not require an entry, may be blank pc program counter slit10 10-bit signed literal ?? {-512...511} slit16 16-bit signed literal ?? {-32768...32767} slit6 6-bit signed literal ?? {-16...16} wb base w register ?? {w0..w15} wd destination w register ?? { wd, [wd], [wd++], [wd--], [++wd], [--wd] } wdo destination w register ? { wnd, [wnd], [wnd++], [wnd--], [++wnd], [--wnd], [wnd+wb] } wm,wn dividend, divisor working r egister pair (direct addressing) wn one of 16 working registers ?? {w0..w15} wnd one of 16 destination working registers ?? {w0..w15} wns one of 16 source working registers ?? {w0..w15} wreg w0 (working register used in file register instructions) ws source w register ?? { ws, [ws], [ws++], [ws--], [++ws], [--ws] } wso source w register ?? { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] }
? 2011 microchip technology inc. ds39995b-page 257 pic24fv32ka304 family table 28-2: instruction set overview assembly mnemonic assembly syntax description # of words # of cycles status flags affected add add f f = f + wreg 1 1 c, dc, n, ov, z add f,wreg wreg = f + wreg 1 1 c, dc, n, ov, z add #lit10,wn wd = lit10 + wd 1 1 c, dc, n, ov, z add wb,ws,wd wd = wb + ws 1 1 c, dc, n, ov, z add wb,#lit5,wd wd = wb + lit5 1 1 c, dc, n, ov, z addc addc f f = f + wreg + (c) 1 1 c, dc, n, ov, z addc f,wreg wreg = f + wreg + (c) 1 1 c, dc, n, ov, z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c, dc, n, ov, z addc wb,ws,wd wd = wb + ws + (c) 1 1 c, dc, n, ov, z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c, dc, n, ov, z and and f f = f .and. wreg 1 1 n, z and f,wreg wreg = f .and. wreg 1 1 n, z and #lit10,wn wd = lit10 .and. wd 1 1 n, z and wb,ws,wd wd = wb .and. ws 1 1 n, z and wb,#lit5,wd wd = wb .and. lit5 1 1 n, z asr asr f f = arithmetic right shift f 1 1 c, n, ov, z asr f,wreg wreg = arithmetic right shift f 1 1 c, n, ov, z asr ws,wd wd = arithmetic right shift ws 1 1 c, n, ov, z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n, z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n, z bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none bsw bsw.c ws,wb write c bit to ws 1 1 none bsw.z ws,wb write z bit to ws 1 1 none btg btg f,#bit4 bit toggle f 1 1 none btg ws,#bit4 bit toggle ws 1 1 none btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none
pic24fv32ka304 family ds39995b-page 258 ? 2011 microchip technology inc. btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws to c 1 1 c btst.z ws,wb bit test ws to z 1 1 z btsts btsts f,#bit4 bit test then set f 1 1 z btsts.c ws,#bit4 bit test ws to c, then set 1 1 c btsts.z ws,#bit4 bit test ws to z, then set 1 1 z call call lit23 call subroutine 2 2 none call wn call indirect subroutine 1 2 none clr clr f f = 0x0000 1 1 none clr wreg wreg = 0x0000 1 1 none clr ws ws = 0x0000 1 1 none clrwdt clrwdt clear watchdog timer 1 1 wdto, sleep com com f f = f 11n, z com f,wreg wreg = f 11n, z com ws,wd wd = ws 11n, z cp cp f compare f with wreg 1 1 c, dc, n, ov, z cp wb,#lit5 compare wb with lit5 1 1 c, dc, n, ov, z cp wb,ws compare wb with ws (wb ? ws) 1 1 c, dc, n, ov, z cp0 cp0 f compare f with 0x0000 1 1 c, dc, n, ov, z cp0 ws compare ws with 0x0000 1 1 c, dc, n, ov, z cpb cpb f compare f with wreg, with borrow 1 1 c, dc, n, ov, z cpb wb,#lit5 compare wb with lit5, with borrow 1 1 c, dc, n, ov, z cpb wb,ws compare wb with ws, with borrow (wb ? ws ? c ) 1 1 c, dc, n, ov, z cpseq cpseq wb,wn compare wb with wn, skip if = 1 1 (2 or 3) none cpsgt cpsgt wb,wn compare wb with wn, skip if > 1 1 (2 or 3) none cpslt cpslt wb,wn compare wb with wn, skip if < 1 1 (2 or 3) none cpsne cpsne wb,wn compare wb with wn, skip if ? 11 (2 or 3) none daw daw wn wn = decimal adjust wn 1 1 c dec dec f f = f ?1 1 1 c, dc, n, ov, z dec f,wreg wreg = f ?1 1 1 c, dc, n, ov, z dec ws,wd wd = ws ? 1 1 1 c, dc, n, ov, z dec2 dec2 f f = f ? 2 1 1 c, dc, n, ov, z dec2 f,wreg wreg = f ? 2 1 1 c, dc, n, ov, z dec2 ws,wd wd = ws ? 2 1 1 c, dc, n, ov, z disi disi #lit14 disable interrupts for k instruction cycles 1 1 none div div.sw wm,wn signed 16/16-bit integer divide 1 18 n, z, c, ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n, z, c, ov div.uw wm,wn unsigned 16/16-bit integer divide 1 18 n, z, c, ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n, z, c, ov exch exch wns,wnd swap wns with wnd 1 1 none ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2011 microchip technology inc. ds39995b-page 259 pic24fv32ka304 family goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none inc inc f f = f + 1 1 1 c, dc, n, ov, z inc f,wreg wreg = f + 1 1 1 c, dc, n, ov, z inc ws,wd wd = ws + 1 1 1 c, dc, n, ov, z inc2 inc2 f f = f + 2 1 1 c, dc, n, ov, z inc2 f,wreg wreg = f + 2 1 1 c, dc, n, ov, z inc2 ws,wd wd = ws + 2 1 1 c, dc, n, ov, z ior ior f f = f .ior. wreg 1 1 n, z ior f,wreg wreg = f .ior. wreg 1 1 n, z ior #lit10,wn wd = lit10 .ior. wd 1 1 n, z ior wb,ws,wd wd = wb .ior. ws 1 1 n, z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n, z lnk lnk #lit14 link frame pointer 1 1 none lsr lsr f f = logical right shift f 1 1 c, n, ov, z lsr f,wreg wreg = logical right shift f 1 1 c, n, ov, z lsr ws,wd wd = logical right shift ws 1 1 c, n, ov, z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n, z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n, z mov mov f,wn move f to wn 1 1 none mov [wns+slit10],wnd move [wns+slit10] to wnd 1 1 none mov f move f to f 1 1 n, z mov f,wreg move f to wreg 1 1 n, z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wns,[wns+slit10] move wns to [wns+slit10] 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 n, z mov.d wns,wd move double from w(ns):w(ns+1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd+1):w(nd) 1 2 none mul mul.ss wb,ws,wnd {wnd+1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd+1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd+1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd+1, wnd} = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none neg neg f f = f + 1 1 1 c, dc, n, ov, z neg f,wreg wreg = f + 1 1 1 c, dc, n, ov, z neg ws,wd wd = ws + 1 1 1 c, dc, n, ov, z nop nop no operation 1 1 none nopr no operation 1 1 none pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd+1) 1 2 none pop.s pop shadow registers 1 1 all push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns+1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
pic24fv32ka304 family ds39995b-page 260 ? 2011 microchip technology inc. pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto, sleep rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none reset reset software device reset 1 1 none retfie retfie return from interrupt 1 3 (2) none retlw retlw #lit10,wn return with literal in wn 1 3 (2) none return return return from subroutine 1 3 (2) none rlc rlc f f = rotate left through carry f 1 1 c, n, z rlc f,wreg wreg = rotate left through carry f 1 1 c, n, z rlc ws,wd wd = rotate left through carry ws 1 1 c, n, z rlnc rlnc f f = rotate left (no carry) f 1 1 n, z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n, z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n, z rrc rrc f f = rotate right through carry f 1 1 c, n, z rrc f,wreg wreg = rotate right through carry f 1 1 c, n, z rrc ws,wd wd = rotate right through carry ws 1 1 c, n, z rrnc rrnc f f = rotate right (no carry) f 1 1 n, z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n, z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n, z se se ws,wnd wnd = sign-extended ws 1 1 c, n, z setm setm f f = ffffh 1 1 none setm wreg wreg = ffffh 1 1 none setm ws ws = ffffh 1 1 none sl sl f f = left shift f 1 1 c, n, ov, z sl f,wreg wreg = left shift f 1 1 c, n, ov, z sl ws,wd wd = left shift ws 1 1 c, n, ov, z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n, z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n, z sub sub f f = f ? wreg 1 1 c, dc, n, ov, z sub f,wreg wreg = f ? wreg 1 1 c, dc, n, ov, z sub #lit10,wn wn = wn ? lit10 1 1 c, dc, n, ov, z sub wb,ws,wd wd = wb ? ws 1 1 c, dc, n, ov, z sub wb,#lit5,wd wd = wb ? lit5 1 1 c, dc, n, ov, z subb subb f f = f ? wreg ? (c ) 1 1 c, dc, n, ov, z subb f,wreg wreg = f ? wreg ? (c ) 1 1 c, dc, n, ov, z subb #lit10,wn wn = wn ? lit10 ? (c ) 1 1 c, dc, n, ov, z subb wb,ws,wd wd = wb ? ws ? (c ) 1 1 c, dc, n, ov, z subb wb,#lit5,wd wd = wb ? lit5 ? (c ) 1 1 c, dc, n, ov, z subr subr f f = wreg ? f 1 1 c, dc, n, ov, z subr f,wreg wreg = wreg ? f 1 1 c, dc, n, ov, z subr wb,ws,wd wd = ws ? wb 1 1 c, dc, n, ov, z subr wb,#lit5,wd wd = lit5 ? wb 1 1 c, dc, n, ov, z subbr subbr f f = wreg ? f ? (c ) 1 1 c, dc, n, ov, z subbr f,wreg wreg = wreg ? f ? (c ) 1 1 c, dc, n, ov, z subbr wb,ws,wd wd = ws ? wb ? (c ) 1 1 c, dc, n, ov, z subbr wb,#lit5,wd wd = lit5 ? wb ? (c ) 1 1 c, dc, n, ov, z swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
? 2011 microchip technology inc. ds39995b-page 261 pic24fv32ka304 family tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none ulnk ulnk unlink frame pointer 1 1 none xor xor f f = f .xor. wreg 1 1 n, z xor f,wreg wreg = f .xor. wreg 1 1 n, z xor #lit10,wn wd = lit10 .xor. wd 1 1 n, z xor wb,ws,wd wd = wb .xor. ws 1 1 n, z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n, z ze ze ws,wnd wnd = zero-extend ws 1 1 c, z, n table 28-2: instruction set overview (continued) assembly mnemonic assembly syntax description # of words # of cycles status flags affected
pic24fv32ka304 family ds39995b-page 262 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 263 pic24fv32ka304 family 29.0 electrical characteristics this section provides an overview of the pic24fv32ka304 family electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic24fv32ka304 family are listed below. exposure to these maximum rating conditions for extended periods may affect device reliability. functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss (pic24fvxxka30x) ....................................................................... -0.3v to +6.5v voltage on v dd with respect to v ss (pic24fxxka30x) .......................................................................... -0.3v to +4.5v voltage on any combined analog and digital pin, with respect to v ss ........................................... -0.3v to (v dd + 0.3v) voltage on any digital only pin with respect to v ss ....................................................................... -0.3v to (v dd + 0.3v) voltage on mclr /v pp pin with respect to v ss ......................................................................................... -0.3v to +9.0v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin (1) ...........................................................................................................................250 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports .............................................................................................. .........................200 ma maximum current sourced by all ports (1) ...............................................................................................................200 ma note 1: maximum allowable current is a function of device maximum power dissipation (see tab l e 2 9- 1 ). notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic24fv32ka304 family ds39995b-page 264 ? 2011 microchip technology inc. 29.1 dc characteristics figure 29-1: pic24fv32k a304 voltage-frequency graph (industrial) figure 29-2: pic24f32ka304 family vo ltage-frequency graph (industrial) frequency voltage (v dd ) 2.00v 32 mhz 5.5v 3.20v 5.5v 8 mhz 3.20v note: for frequencies between 8 mhz and 32 mhz, f max = 20 mhz *(v dd ? 2.0) + 8 mhz. frequency voltage (v dd ) 1.80v 32 mhz 3.60v 3.00v 3.60v 8 mhz 3.00v note: for frequencies between 8 mhz and 32 mhz, f max = 20 mhz * (v dd ? 1.8) + 8 mhz.
? 2011 microchip technology inc. ds39995b-page 265 pic24fv32ka304 family table 29-1: thermal operating conditions rating symbol min typ max unit operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? ? i oh ) p d p int + p i / o w i/o pin power dissipation: p i / o = ? ({v dd ? v oh } x i oh ) + ? (v ol x i ol ) maximum allowed power dissipation p dmax (t j ? t a )/ ? ja w table 29-2: thermal packaging characteristics characteristic symbol typ max unit notes package thermal resistance, 20-pin spdip ? ja 62.4 ? c/w 1 package thermal resistance, 28-pin spdip ? ja 60 ? c/w 1 package thermal resistance, 20-pin ssop ? ja 108 ? c/w 1 package thermal resistance, 28-pin ssop ? ja 71 ? c/w 1 package thermal resistance, 20-pin soic ? ja 75 ? c/w 1 package thermal resistance, 28-pin soic ? ja 80.2 ? c/w 1 package thermal resistance, 20-pin qfn ? ja 43 ? c/w 1 package thermal resistance, 28-pin qfn ? ja 32 ? c/w 1 package thermal resistance, 44-pin qfn ? ja 29 ? c/w 1 package thermal resistance, 48-pin uqfn ? ja ??c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ? ja ) numbers are achieved by package simulations. table 29-3: dc characteristics: temperature and voltage specifications dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial para m no. symbol characteristic min typ (1) max units conditions dc10 v dd supply voltage 1.8 ? 3.6 v for f devices 2.0 ? 5.5v v for fv devices dc12 v dr ram data retention voltage (2) 1.5 ? ? v dc16 v por v dd start voltage to ensure internal power-on reset signal v ss ?0.7v dc17 sv dd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms 0-3.3v in 0.1s 0-2.5v in 60 ms note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: this is the limit to which v dd can be lowered without losing ram data.
pic24fv32ka304 family ds39995b-page 266 ? 2011 microchip technology inc. table 29-4: high/low?voltage detect characteristics table 29-5: bor trip points standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min typ max units conditions dc18 v hlvd hlvd voltage on v dd transition hlvdl<3:0> = 0000 (2) ??1.90v hlvdl<3:0> = 0001 1.88 ? 2.13 v hlvdl<3:0> = 0010 2.09 ? 2.35 v hlvdl<3:0> = 0011 2.25 ? 2.53 v hlvdl<3:0> = 0100 2.35 ? 2.62 v hlvdl<3:0> = 0101 2.55 ? 2.84 v hlvdl<3:0> = 0110 2.80 ? 3.10 v hlvdl<3:0> = 0111 2.95 ? 3.25 v hlvdl<3:0> = 1000 3.09 ? 3.41 v hlvdl<3:0> = 1001 3.27 ? 3.59 v hlvdl<3:0> = 1010 (1) 3.46 ? 3.79 v hlvdl<3:0> = 1011 (1) 3.62 ? 4.01 v hlvdl<3:0> = 1100 (1) 3.91 ? 4.26 v hlvdl<3:0> = 1101 (1) 4.18 ? 4.55 v hlvdl<3:0> = 1110 (1) 4.49 ? 4.87 v note 1: these trip points should not be used on pic24f32ka304 devices. 2: this trip point should not be used on pic24fvxxka30x devices. standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ max units conditions dc19 bor voltage on v dd transition borv = 00 ? ? ? ? valid for lpbor and dsbor, note 1 borv = 01 2.90 3 3.38 v borv = 10 2.53 2.7 3.07 v borv = 11 1.75 1.85 2.05 v note 2 borv = 11 1.95 2.05 2.16 v note 3 note 1: lpbor re-arms the por circuit but does not cause a bor. 2: valid for pic24f (3.3v) devices. 3: valid for pic24fv (5v) devices.
? 2011 microchip technology inc. ds39995b-page 267 pic24fv32ka304 family table 29-6: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical max units conditions i dd current dc20 pic24fv32ka3xx 269.00 ? a -40c 2.0v 0.5 mips, fosc = 1 mhz dc20a ? +25c dc20b ? +60c dc20c 450.00 +85c dc20d 465.00 ? a -40c 5.0v dc20e ? +25c dc20f ? +60c dc20g 830.00 +85c dc20h pic24f32ka3xx 200.00 ? a -40c 1.8v dc20i ? +25c dc20j ? +60c dc20k 330.00 +85c dc20l 410.00 ? a -40c 3.3v dc20m ? +25c dc20n ? +60c dc20o 750.00 +85c dc22 pic24fv32ka3xx 490.00 ? a -40c 2.0v 1 mips, fosc = 2 mhz dc22a ? +25c dc22b ? +60c dc22c ? +85c dc22d 880.00 ? a -40c 5.0v dc22e ? +25c dc22f ? +60c dc22g ? +85c dc22h pic24f32ka3xx 407.00 ? a -40c 1.8v dc22i ? +25c dc22j ? +60c dc22k ? +85c dc22l 800.00 ? a -40c 3.3v dc22m ? +25c dc22n ? +60c dc22o ? +85c legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices.
pic24fv32ka304 family ds39995b-page 268 ? 2011 microchip technology inc. i dd current (continued) dc24 pic24fv32ka3xx 13.00 ? ma -40c 5.0v 16 mips, fosc = 32 mhz dc24a ? +25c dc24b ? +60c dc24c 20.00 +85c dc24d pic24f32ka3xx 12.00 ? ma -40c 3.3v dc24e ? +25c dc24f ? +60c dc24g 18.00 +85c dc26 pic24fv32ka3xx 2.00 ? ma -40c 2.0v frc (4 mips), fosc = 8 mhz dc26a ? +25c dc26b ? +60c dc26c ? +85c dc26d 3.50 ? ma -40c 5.0v dc26e ? +25c dc26f ? +60c dc26g ? +85c dc26h pic24f32ka3xx 1.80 ? ma -40c 1.8v dc26i ? +25c dc26j ? +60c dc26k ? +85c dc26l 3.40 ? ma -40c 3.3v dc26m ? +25c dc26n ? +60c dc26o ? +85c dc30 pic24fv32ka3xx 48.00 ? a -40c 2.0v lprc (15.5 kips), fosc = 31 khz dc30a ? +25c dc30b ? +60c dc30c 250.00 +85c dc30d 75.00 ? a -40c 5.0v dc30e ? +25c dc30f ? +60c dc30g 275.00 +85c dc30h pic24f32ka3xx 8.10 ? a -40c 1.8v dc30i ? +25c dc30j ? +60c dc30k 28.00 +85c dc30l 13.50 ? a -40c 3.3v dc30m ? +25c dc30n ? +60c dc30o 55.00 +85c table 29-6: dc characteristics: operating current (i dd ) (continued) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical max units conditions legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices.
? 2011 microchip technology inc. ds39995b-page 269 pic24fv32ka304 family table 29-7: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical max units conditions idle current (i idle ) dc40 pic24fv32ka3xx 120.00 ? a -40c 2.0v 0.5 mips, fosc = 1 mhz dc40a ? +25c dc40b ? +60c dc40c 200.00 +85c dc40d 160.00 ? a -40c 5.0v dc40e ? +25c dc40f ? +60c dc40g 430.00 +85c dc40h pic24f32ka3xx 50.00 ? a -40c 1.8v dc40i ? +25c dc40j ? +60c dc40k 100.00 +85c dc40l 90.00 ? a -40c 3.3v dc40m ? +25c dc40n ? +60c dc40o 370.00 +85c dc42 pic24fv32ka3xx 165.00 ? a -40c 2.0v 1 mips, fosc = 2 mhz dc42a ? +25c dc42b ? +60c dc42c ? +85c dc42d 260.00 ? a -40c 5.0v dc42e ? +25c dc42f ? +60c dc42g ? +85c dc42h pic24f32ka3xx 95.00 ? a -40c 1.8v dc42i ? +25c dc42j ? +60c dc42k ? +85c dc42l 180.00 ? a -40c 3.3v dc42m ? +25c dc42n ? +60c dc42o ? +85c dc44 pic24fv32ka3xx 3.10 ? ma -40c 5.0v 16 mips, fosc = 32 mhz dc44a ? +25c dc44b ? +60c dc44c 6.50 +85c dc44d pic24f32ka3xx 2.90 ? ma -40c 3.3v dc44e ? +25c dc44f ? +60c dc44g 6.00 +85c legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices.
pic24fv32ka304 family ds39995b-page 270 ? 2011 microchip technology inc. idle current (i idle ) (continued) dc46 pic24fv32ka3xx 0.65 ? ma -40c 2.0v frc (4 mips), fosc = 8 mhz dc46a ? +25c dc46b ? +60c dc46c ? +85c dc46d 1.00 ? ma -40c 5.0v dc46e ? +25c dc46f ? +60c dc46g ? +85c dc46h pic24f32ka3xx 0.55 ? ma -40c 1.8v dc46i ? +25c dc46j ? +60c dc46k ? +85c dc46l 1.00 ? ma -40c 3.3v dc46m ? +25c dc46n ? +60c dc46o ? +85c dc50 pic24fv32ka3xx 60.00 ? a -40c 2.0v lprc (15.5 kips), fosc = 31 khz dc50a ? +25c dc50b ? +60c dc50c 200.00 +85c dc50d 70.00 ? a -40c 5.0v dc50e ? +25c dc50f ? +60c dc50g 225.00 +85c dc50h pic24f32ka3xx 2.20 ? a -40c 1.8v dc50i ? +25c dc50j ? +60c dc50k 18.00 +85c dc50l 4.00 ? a -40c 3.3v dc50m ? +25c dc50n ? +60c dc50o 40.00 +85c table 29-7: dc characteristics: idle current (i idle ) (continued) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical max units conditions legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices.
? 2011 microchip technology inc. ds39995b-page 271 pic24fv32ka304 family table 29-8: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical (1) max units conditions power-down current (i pd ) dc60 pic24fv32ka3xx 6.00 ? a -40c 2.0v sleep mode (2) dc60a 8.00 +25c dc60b 8.50 +60c dc60c 9.00 +85c dc60d 6.00 ? a -40c 5.0v dc60e 8.00 +25c dc60f 9.00 +60c dc60g 10.00 +85c dc60h pic24f32ka3xx 0.025 ? a -40c 1.8v dc60i 0.80 +25c dc60j 1.50 +60c dc60k 2.00 +85c dc60l 0.040 ? a -40c 3.3v dc60m 1.00 +25c dc60n 2.00 +60c dc60o 3.00 +85c dc61 pic24fv32ka3xx 0.25 ? a -40c 2.0v low-voltage sleep mode (2) dc61a ? +25c dc61b ? +60c dc61c ? +85c dc61d 0.35 ? a -40c 5.0v dc61e ? +25c dc61f ? +60c dc61g 3.00 +85c legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices. note 1: data in the typical column is at 3.3v, 25c (p ic24f32ka3xx); 5.0v, 25c (pic24fv32ka3xx) unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as outputs and set low, pmslp is set to ? 0 ?, and wdt, etc., are all switched off. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: current applies to sleep only. 5: current applies to sleep and deep sleep. 6: current applies to deep sleep only.
pic24fv32ka304 family ds39995b-page 272 ? 2011 microchip technology inc. power-down current (i pd ) (continued) dc70 pic24fv32ka3xx 0.03 ? a -40c 2.0v deep sleep mode dc70a ? +25c dc70b ? +60c dc70c ? +85c dc70d 0.10 ? a -40c 5.0v dc70e ? +25c dc70f ? +60c dc70g 1.20 +85c dc70h pic24f32ka3xx 0.02 ? a -40c 1.8v dc70i ? +25c dc70j ? +60c dc70k ? +85c dc70l 0.08 ? a -40c 3.3v dc70m ? +25c dc70n ? +60c dc70o 1.20 +85c table 29-8: dc characteristics: power-down current (i pd ) (continued) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical (1) max units conditions legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices. note 1: data in the typical column is at 3.3v, 25c (p ic24f32ka3xx); 5.0v, 25c (pic24fv32ka3xx) unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as outputs and set low, pmslp is set to ? 0 ?, and wdt, etc., are all switched off. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: current applies to sleep only. 5: current applies to sleep and deep sleep. 6: current applies to deep sleep only.
? 2011 microchip technology inc. ds39995b-page 273 pic24fv32ka304 family power-down current (i pd ) (continued) dc71 pic24fv32ka3xx 0.50 ? a -40c 2.0v watchdog timer current: ? wdt (3,4) dc71a ? +25c dc71b ? +60c dc71c ? +85c dc71d 0.70 ? a -40c 5.0v dc71e ? +25c dc71f ? +60c dc71g 1.5 +85c dc71h pic24f32ka3xx 0.50 ? a -40c 1.8v dc71i ? +25c dc71j ? +60c dc71k ? +85c dc71l 0.70 ? a -40c 3.3v dc71m ? +25c dc71n ? +60c dc71o 1.5 +85c dc72 pic24fv32ka3xx 0.80 ? a -40c 2.0v 32 khz crystal with rtcc, dswdt or timer1: ? sosc; (soscsel = 0 ) (3,5) dc72a ? +25c dc72b ? +60c dc72c ? +85c dc72d 1.50 ? a -40c 5.0v dc72e ? +25c dc72f ? +60c dc72g 2.0 +85c dc72h pic24f32ka3xx 0.70 ? a -40c 1.8v dc72i ? +25c dc72j ? +60c dc72k ? +85c dc72l 1.00 ? a -40c 3.3v dc72m ? +25c dc72n ? +60c dc72o 1.5 +85c table 29-8: dc characteristics: power-down current (i pd ) (continued) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical (1) max units conditions legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices. note 1: data in the typical column is at 3.3v, 25c (p ic24f32ka3xx); 5.0v, 25c (pic24fv32ka3xx) unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as outputs and set low, pmslp is set to ? 0 ?, and wdt, etc., are all switched off. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: current applies to sleep only. 5: current applies to sleep and deep sleep. 6: current applies to deep sleep only.
pic24fv32ka304 family ds39995b-page 274 ? 2011 microchip technology inc. power-down current (i pd ) (continued) dc75 pic24fv32ka3xx 5.40 ? a -40c 2.0v ? hlvd (3,4) dc75a ? +25c dc75b ? +60c dc75c ? +85c dc75d 8.10 ? a -40c 5.0v dc75e ? +25c dc75f ? +60c dc75g 14.00 +85c dc75h pic24f32ka3xx 4.90 ? a -40c 1.8v dc75i ? +25c dc75j ? +60c dc75k ? +85c dc75l 7.50 ? a -40c 3.3v dc75m ? +25c dc75n ? +60c dc75o 14.00 +85c dc76 pic24fv32ka3xx 5.60 ? a -40c 2.0v ? bor (3,4) dc76a ? +25c dc76b ? +60c dc76c ? +85c dc76d 6.50 ? a -40c 5.0v dc76e ? +25c dc76f ? +60c dc76g 11.20 +85c dc76h pic24f32ka3xx 5.60 ? a -40c 1.8v dc76i ? +25c dc76j ? +60c dc76k ? +85c dc76l 6.00 ? a -40c 3.3v dc76m ? +25c dc76n ? +60c dc76o 11.20 +85c table 29-8: dc characteristics: power-down current (i pd ) (continued) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical (1) max units conditions legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices. note 1: data in the typical column is at 3.3v, 25c (p ic24f32ka3xx); 5.0v, 25c (pic24fv32ka3xx) unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as outputs and set low, pmslp is set to ? 0 ?, and wdt, etc., are all switched off. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: current applies to sleep only. 5: current applies to sleep and deep sleep. 6: current applies to deep sleep only.
? 2011 microchip technology inc. ds39995b-page 275 pic24fv32ka304 family power-down current (i pd ) (continued) dc78 pic24fv32ka3xx 0.03 ? a -40c 2.0v ? lpbor/deep sleep bor (3,5) dc78a ? +25c dc78b ? +60c dc78c ? +85c dc78d 0.05 ? a -40c 5.0v dc78e ? +25c dc78f ? +60c dc78g 0.20 +85c dc78h pic24f32ka3xx 0.03 ? a -40c 1.8v dc78i ? +25c dc78j ? +60c dc78k ? +85c dc78l 0.05 ? a -40c 3.3v dc78m ? +25c dc78n ? +60c dc78o 0.20 +85c dc80 pic24fv32ka3xx 0.20 ? a -40c 2.0v deep sleep wdt: ? dswdt (lprc) (3,6) dc80a ? +25c dc80b ? +60c dc80c ? +85c dc80d 0.70 ? a -40c 5.0v dc80e ? +25c dc80f ? +60c dc80g 1.5 +85c dc80h pic24f32ka3xx 0.20 ? a -40c 1.8v dc80i ? +25c dc80j ? +60c dc80k ? +85c dc80l 0.35 ? a -40c 3.3v dc80m ? +25c dc80n ? +60c dc80o 0.8 +85c table 29-8: dc characteristics: power-down current (i pd ) (continued) dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial parameter no. device typical (1) max units conditions legend: unshaded rows are pic24f32ka3xx devices, and shaded rows are pic24fv32ka3xx devices. note 1: data in the typical column is at 3.3v, 25c (p ic24f32ka3xx); 5.0v, 25c (pic24fv32ka3xx) unless otherwise stated. parameters are for design guidance only and are not tested. 2: base i pd is measured with all peripherals and clocks shut down. all i/os are configured as outputs and set low, pmslp is set to ? 0 ?, and wdt, etc., are all switched off. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: current applies to sleep only. 5: current applies to sleep and deep sleep. 6: current applies to deep sleep only.
pic24fv32ka304 family ds39995b-page 276 ? 2011 microchip technology inc. table 29-9: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units conditions v il input low voltage (4) ???? di10 i/o pins v ss ? 0.2 v dd v di15 mclr v ss ? 0.2 v dd v di16 osci (xt mode) v ss ? 0.2 v dd v di17 osci (hs mode) v ss ? 0.2 v dd v di18 i/o pins with i 2 c? buffer v ss ? 0.3 v dd v smbus disabled di19 i/o pins with smbus buffer v ss ? 0.8 v smbus enabled v ih input high voltage (4) ???? di20 i/o pins: with analog functions digital only 0.8 v dd 0.8 v dd ? ? v dd v dd v v di25 mclr 0.8 v dd ?v dd v di26 osci (xt mode) 0.7 v dd ?v dd v di27 osci (hs mode) 0.7 v dd ?v dd v di28 i/o pins with i 2 c buffer: with analog functions digital only 0.7 v dd 0.7 v dd ? ? v dd v dd v v di29 i/o pins with smbus 2.1 ? v dd v2.5v ? v pin ? v dd di30 i cnpu cnx pull-up current 50 250 500 ? av dd = 3.3v, v pin = v ss i il input leakage current (2,3) di50 i/o ports ? 0.05 0.1 ? av ss ? v pin ? v dd , pin at high-impedance di55 mclr ??0.1 ? av ss ?? v pin ?? v dd di56 osci ? ? 5 ? av ss ?? v pin ?? v dd , xt and hs modes note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: refer to ta b l e 1 - 3 for i/o pin buffer types.
? 2011 microchip technology inc. ds39995b-page 277 pic24fv32ka304 family table 29-10: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units conditions v ol output low voltage ?? do10 all i/o pins ? ? 0.4 v i ol = 8.0 ma v dd = 4.5v ??0.4vi ol = 4.0 ma v dd = 3.6v ??0.4vi ol = 3.5 ma v dd = 2.0v do16 osc2/clko ? ? 0.4 v i ol = 2.0 ma v dd = 4.5v ??0.4vi ol = 1.2 ma v dd = 3.6v ??0.4vi ol = 0.4 ma v dd = 2.0v v oh output high voltage do20 all i/o pins 3.8 ? ? v i oh = -3.5 ma v dd = 4.5v 3??vi oh = -3.0 ma v dd = 3.6v 1.6 ? ? v i oh = -1.0 ma v dd = 2.0v do26 osc2/clko 3.8 ? ? v i oh = -2.0 ma v dd = 4.5v 3??vi oh = -1.0 ma v dd = 3.6v 1.6 ? ? v i oh = -0.5 ma v dd = 2.0v note 1: data in ?typ? column is at 25c unless otherwise stated. parameters are for design guidance only and are not tested. table 29-11: dc characteristics: program memory dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units conditions program flash memory d130 e p cell endurance 10,000 (2) ??e/w d131 v pr v dd for read v min ?3.6vv min = minimum operating voltage d133a t iw self-timed write cycle time ?2?ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?10?ma note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. 2: self-write and block erase.
pic24fv32ka304 family ds39995b-page 278 ? 2011 microchip technology inc. table 29-13: comparat or dc specifications table 29-14: comparator voltag e reference dc specifications table 29-12: dc characteristics: data eeprom memory dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units conditions data eeprom memory d140 e pd cell endurance 100,000 ? ? e/w d141 v prd v dd for read v min ?3.6vv min = minimum operating voltage d143a t iwd self-timed write cycle time ?4 ?ms d143b t ref number of total write/erase cycles before refresh ?10m ?e/w d144 t retdd characteristic retention 40 ? ? year provided no other specifications are violated d145 i ddpd supply current during programming ?7 ?ma note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. operating conditions: 2.0v < v dd < 3.6v, -40c < t a < +85c (unless otherwise stated) param no. symbol characteristic min typ max units comments d300 v ioff input offset voltage* ? 20 40 mv d301 v icm input common mode voltage* 0 ? v dd v d302 cmrr common mode rejection ratio* 55 ? ? db * parameters are characterized but not tested. operating conditions: 2.0v < v dd < 3.6v, -40c < t a < +85c (unless otherwise stated) param no. symbol characteristic min typ max units comments vrd310 cv res resolution ? ? v dd /32 lsb vrd311 cvr aa absolute accuracy ? ? av dd ? 1.5 lsb vrd312 cvr ur unit resistor value (r) ? 2k ? ?
? 2011 microchip technology inc. ds39995b-page 279 pic24fv32ka304 family table 29-15: internal voltag e regulator specifications operating conditions: -40c < t a < +85c (unless otherwise stated) param no. symbol characteristics min typ max units comments v bg band gap reference voltage 0.973 1.024 1.075 v t bg band gap reference start-up time ?1?ms v rgout regulator output voltage 3.1 3.3 3.6 v c efc external filter capacitor value 4.7 10 ? ? f series resistance < 3 ohm recommended; < 5 ohm required. v lvr low-voltage regulator output voltage ?2.6?v table 29-16: ctmu current source specifications dc characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units comments conditions i out 1 ctmu current source, base range ? 550 ? na ctmuicon<1:0> = 00 2.5v < v dd < v ddmax i out 2 ctmu current source, 10x range ?5.5? ? a ctmuicon<1:0> = 01 i out 3 ctmu current source, 100x range ?55? ? a ctmuicon<1:0> = 10 i out 4 ctmu current source, 1000x range ? 550 ? ? a ctmuicon<1:0> = 11, note 2 v f temperature diode forward voltage ?.76? v v ? voltage change per degree celsius ?3?mv/c note 1: nominal value at center point of current trim range (ctmuicon<7:2> = 000000 ). on pic24f32ka parts, the current output is limited to the typ. current value when iot4 is chosen. 2: do not use this current range with temperature sensing diode.
pic24fv32ka304 family ds39995b-page 280 ? 2011 microchip technology inc. 29.2 ac characteristics and timing parameters the information contained in this section defines the pic24fv32ka304 family ac characteristics and timing parameters. table 29-17: temperature and vo ltage specifications ? ac figure 29-3: load conditions for device timing specifications table 29-18: capacitiv e loading requirements on output pins ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature-40c ? t a ? +85c for industrial operating voltage v dd range as described in section 29.1 ?dc characteristics? . param no. symbol characteristic min typ (1) max units conditions do50 c osc 2 osco/clko pin ? ? 15 pf in xt and hs modes when external clock is used to drive osci do56 c io all i/o pins and osco ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all pins except osco 15 pf for osco output load condition 1 ? for all pins except osco load condition 2 ? for osco
? 2011 microchip technology inc. ds39995b-page 281 pic24fv32ka304 family figure 29-4: external clock timing osci clko q4 q1 q2 q3 q4 q1 os20 os25 os30 os30 os40 os41 os31 os31 q1 q2 q3 q4 q2 q3 table 29-19: external clo ck timing requirements ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units conditions os10 f osc external clki frequency (external clocks allowed only in ec mode) dc 4 ? ? 32 8 mhz mhz ec ecpll oscillator frequency 0.2 4 4 31 ? ? ? ? 4 25 8 33 mhz mhz mhz khz xt hs xtpll sosc os20 t osc t osc = 1/f osc ? ? ? ? see parameter os10 for f osc value os25 t cy instruction cycle time (2) 62.5 ? dc ns os30 tosl, to s h external clock in (osci) high or low time 0.45 x t osc ??nsec os31 tosr, to s f external clock in (osci) rise or fall time ??20nsec os40 tckr clko rise time (3) ?610ns os41 tckf clko fall time (3) ?610ns note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: instruction cycle period (t cy ) equals two times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osci/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osco pin. clko is low for the q1-q2 period (1/2 t cy ) and high for the q3-q4 period (1/2 t cy ).
pic24fv32ka304 family ds39995b-page 282 ? 2011 microchip technology inc. table 29-20: pll clock ti ming specifications ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic (1) min typ (2) max units conditions os50 f plli pll input frequency range 4 ? 8 mhz ecpll, hspll modes, -40c ? t a ? +85c os51 f sys pll output frequency range 16 ? 32 mhz -40c ? t a ? +85c os52 t lock pll start-up time (lock time) ?1 2ms os53 d clk clko stability (jitter) -2 1 2 % measured over 100 ms period note 1: these parameters are characterized but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. table 29-21: ac characteristics: internal frc accuracy ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. characteristic min typ max units conditions f20 internal frc accuracy @ 8 mhz (1) frc -2 ? +2 % +25c 3.0v ? v dd ? 3.6v, f device 3.2v ? v dd ? 5.5v, fv device -5 ? +5 % -40c ? t a ?? +85c 1.8v ? v dd ? 3.6v, f device 2.0v ? v dd ? 5.5v, fv device note 1: frequency calibrated at 25c and 3.3v. osctun bits can be used to compensate for temperature drift. table 29-22: ac characteristics: internal rc accuracy ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. characteristic min typ max units conditions lprc @ 31 khz (1) f21 -15 ? 15 % note 1: change of lprc frequency as v dd changes. table 29-23: internal rc os cillator specifications ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym characteristic (1) min typ max units conditions t frc frc start-up time ? 5 ? ? s t lprc lprc start-up time ? 70 ? ? s
? 2011 microchip technology inc. ds39995b-page 283 pic24fv32ka304 family figure 29-5: clko and i/o ti ming characteristics note: refer to figure 29-3 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 table 29-24: clko and i/ o timing requirements ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. sym characteristic min typ (1) max units conditions do31 t io r port output rise time ? 10 25 ns do32 t io f port output fall time ? 10 25 ns di35 t inp intx pin high or low time (output) 20 ? ? ns di40 t rbp cnx high or low time (input) 2??t cy note 1: data in ?typ? column is at 3.3v, 25c (p ic24f32ka3xx); 5.0v, 25c (pic24fv32ka3xx), unless otherwise stated.
pic24fv32ka304 family ds39995b-page 284 ? 2011 microchip technology inc. table 29-25: comp arator timings table 29-26: comparator voltage re ference settling time specifications param no. symbol characteristic min typ max units comments 300 t resp response time* (1) ? 150 400 ns 301 t mc 2 ov comparator mode change to output valid * ?? 10 ? s * parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . param no. symbol characteristic min typ max units comments vr310 t set settling time (1) ??10 ? s note 1: settling time measured while cvrss = 1 and cvr<3:0> bits transition from ? 0000 ? to ? 1111 ?.
? 2011 microchip technology inc. ds39995b-page 285 pic24fv32ka304 family table 29-27: adc mo dule specifications ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 1.8 ? lesser of v dd + 0.3 or 3.6 v ad02 av ss module v ss supply v ss ? 0.3 ? v ss + 0.3 v reference inputs ad05 v refh reference voltage high av ss + 1.7 ? av dd v ad06 v refl reference voltage low av ss ?av dd ? 1.7 v ad07 v ref absolute reference voltage av ss ? 0.3 ? av dd + 0.3 v analog input ad10 v inh -v inl full-scale input span v refl ?v refh v (note 2) ad11 v in absolute input voltage av ss ? 0.3 ? av dd + 0.3 v ad12 v inl absolute v inl input voltage av ss ? 0.3 av dd /2 v ad17 r in recommended impedance of analog voltage source ? ? 2.5k ? 12-bit adc accuracy ad20b n r resolution ? 12 ? bits ad21b inl integral nonlinearity ? 1 9 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad22b dnl differential nonlinearity ? 1 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad23b g err gain error ? 1 9 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad24b e off offset error ? 1 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 5v ad25b monotonicity (1) ? ? ? ? guaranteed note 1: the adc conversion result never decreases with an increase in the input voltage. 2: measurements are taken with external v ref + and v ref - used as the adc voltage reference.
pic24fv32ka304 family ds39995b-page 286 ? 2011 microchip technology inc. table 29-28: adc conversion timing requirements (1) ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min. typ max. units conditions clock parameters ad50 t ad adc clock period 75 ? ? ns t cy = 75 ns, ad1con3 in default state ad51 t rc adc internal rc oscillator period ?250 ? ns conversion rate ad55 t conv conversion time ? 12 ? t ad ad56 f cnv throughput rate ? ? 100 ksps av dd ? 2.7v ad57 t samp sample time ? 1 ? t ad ad58 t acq acquisition time 750 ? ? ns (note 2) ad59 t swc switching time from convert to sample ?? (note 3) ad60 t dis discharge time 0.5 ? ? t ad clock parameters ad61 t pss sample start delay from setting sample bit (samp) 2? 3 t ad note 1: because the sample caps will eventually lose charge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 2: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). 3: on the following cycle of the device clock.
? 2011 microchip technology inc. ds39995b-page 287 pic24fv32ka304 family table 29-29: reset, watchdog timer, oscill ator start-up timer, power-up timer, and brown-out reset timing requirements ac characteristics standard operating conditions: 1.8v to 3.6v pic24f32ka3xx 2.0v to 5.5v pic24fv32ka3xx operating temperature -40c ? t a ? +85c for industrial param no. symbol characteristic min. typ (1) max. units conditions sy10 tmcl mclr pulse width (low) 2 ? ? ? s sy11 t pwrt power-up timer period 50 64 90 ms sy12 t por power-on reset delay 1 5 10 ? s sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset ? ? 100 ns sy20 t wdt watchdog timer time-out period 0.85 1.0 1.15 ms 1.32 prescaler 3.4 4.0 4.6 ms 1:128 prescaler sy25 t bor brown-out reset pulse width 1? ? ? s sy45 t rst internal state reset time ? 5 ? ? s sy55 t lock pll start-up time ? 100 ? ? s sy65 t ost oscillator start-up time ? 1024 ? t osc sy70 t dswu wake-up from deep sleep time ?100 ? ? s based on full discharge of 10 ? f capacitor on v cap . includes t por and t rst sy71 t pm program memory wake-up time ?1 ? ? ssleep wake-up with pmslp = 0 sy72 t lvr low-voltage regulator wake-up time ?250 ? ? s note 1: data in ?typ? column is at 3.3v, 25c unless otherwise stated.
pic24fv32ka304 family ds39995b-page 288 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 289 pic24fv32ka304 family 30.0 packaging information 30.1 package marking information legend: xx...x product-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 20 -lea d pdip ( 300 mil ) exa mple 28-lead spdip (.300?) example 28-lead ssop (5.30 mm) example 20-lead ssop (5.30 mm) example pic24fv32ka301 -i/p 1010017 3 e pic24fv32ka302 -i/sp 1010017 3 e pic24fv32ka 301-i/ss 1010017 3 e pic24fv32ka 302-i/ss 1010017 3 e
pic24fv32ka304 family ds39995b-page 290 ? 2011 microchip technology inc. 20-lea d soic ( 7.50 mm) exam pl e 28-lead soic ( 7.50 mm) exam pl e 28 -l ea d qfn (6 x6 mm ) examp le pic24fv32ka301 -i/so 1010017 3 e pic24fv32ka302 -i/so 1010017 3 e pic24fv32ka 302-i/ml 1010017 3 e
? 2011 microchip technology inc. ds39995b-page 291 pic24fv32ka304 family 48-lead uqfn (6x6x0.5 mm) example pic24fv32ka 304-i/mv 1010017 3 e 44-lead qfn (8x8x0.9 mm) example 44-lead tqfp (10x10x1 mm) example pic24fv32ka 304-i/ml 1010017 3 e pic24fv32ka 304-i/pt 1010017 3 e
pic24fv32ka304 family ds39995b-page 292 ? 2011 microchip technology inc. 30.2 package details the following sections give the technical details of the packages.

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pic24fv32ka304 family ds39995b-page 300 ? 2011 microchip technology inc.
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? 2011 microchip technology inc. ds39995b-page 309 pic24fv32ka304 family note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic24fv32ka304 family ds39995b-page 310 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 311 pic24fv32ka304 family appendix a: revision history revision a (march 2011) original data sheet for the pic24fv32ka304 family of devices. revision b (april 2011) section 25.0 ?charge time measurement unit (ctmu)? was revised to change the description of the irng bits in ctmuicon ( register 25-3 ). setting ? 01 ? is the base current level (0.55 ? a nominal) and setting ? 00 ? is 1000x base current. section 29.0 ?electrical characteristics? was revised to change the following typical i pd specifications: ? dc20h/i/j/k from 204 ? a to 200 ? a ? dc60h/i/j/k from 0.15 ? a to 0.025 ? a ? dc60l/m/n/o from 0.25 ? a to 0.040 ? a ? dc72h/i/j/k from 0.80 ? a to 0.70 ? a
pic24fv32ka304 family ds39995b-page 312 ? 2011 microchip technology inc. notes:
? 2011 microchip technology inc. ds39995b-page 313 pic24fv32ka304 family index a a/d control registers ..................................................... 214 ad1chith/l .................................................... 214 ad1chs .......................................................... 214 ad1con1 ........................................................ 214 ad1con2 ........................................................ 214 ad1con3 ........................................................ 214 ad1con5 ........................................................ 214 ad1cssl/h ..................................................... 214 ad1ctmenh/l ............................................... 214 conversion timing requirements .................... 286, 288 module specifications .............................................. 285 result buffers .......................................................... 214 sampling requirements ........................................... 223 transfer function ..................................................... 224 ac characteristics capacitive loading requirements on output pins ...................................................... 280 comparator .............................................................. 284 comparator voltage reference settling time ......... 284 internal rc accuracy ............................................... 282 internal rc oscillator specifications ........................ 282 load conditions and requirements ......................... 280 temperature and voltage specifications ................. 280 assembler mpasm assembler .................................................. 252 b baud rate generator setting as a bus master ........................................... 175 block diagrams 12-bit a/d converter ................................................ 212 12-bit a/d converter analog input model ................ 223 16-bit asynchronous timer3 and timer5 ................ 147 16-bit synchronous timer2 and timer4 .................. 147 16-bit timer1 ........................................................... 143 accessing program memory with table instructions ........................................................ 56 call stack frame ..................................................... 53 comparator module ................................................. 225 comparator voltage reference ............................... 229 cpu programmer?s model ......................................... 33 crc module ............................................................ 203 crc shift engine ..................................................... 203 ctmu connections and internal configuration for capacitance measurement ......................... 232 ctmu typical connections and internal configuration for pulse delay generation ....... 233 ctmu typical connections and internal configuration for time measurement .............. 233 data access from program space address generation ......................................................... 54 data eeprom addressing with tblpag and nvm registers ................................................... 69 high/low-voltage detect (hlvd) ............................ 209 i 2 c module ............................................................... 174 individual comparator configurations ...................... 226 input capture ........................................................... 151 on-chip regulator connections .............................. 248 output compare (16-bit mode) ................................ 156 output compare (double-buffered, 16-bit pwm mode) .......................................... 158 pic24f cpu core ..................................................... 32 pic24fv32ka304 family (general) ......................... 17 psv operation ........................................................... 57 reset system ............................................................ 73 rtcc ....................................................................... 189 serial resistor ......................................................... 133 shared i/o port structure ........................................ 139 simplified uart ...................................................... 181 spix module (enhanced buffer mode) .................... 167 spix module (standard buffer mode) ...................... 166 system clock ........................................................... 117 table register addressing ........................................ 59 timer2/3, timer4/5 (32-bit) ..................................... 146 watchdog timer (wdt) ........................................... 249 brown-out reset trip points ............................................................... 266 c c compilers mplab c18 ............................................................. 252 charge time measurement unit. see ctmu. code examples data eeprom bulk erase ........................................ 71 data eeprom unlock sequence ............................. 67 erasing a program memory row, ?c? language code ............................................ 63 erasing a program memory row, assembly language code ................................................. 62 i/o port write/read ................................................. 142 initiating a programming sequence, ?c? language code ............................................ 64 initiating a programming sequence, assembly language code ................................ 64 loading the write buffers, ?c? language code ......... 64 loading the write buffers, assembly language code ................................................. 63 programming a single word of flash program memory ............................................... 65 pwrsav instruction syntax ................................... 127 reading the data eeprom using the tblrd command ............................................. 72 sequence for clock switching ................................. 124 setting the rtcwren bit ....................................... 190 single-word erase .................................................... 70 single-word write to data eeprom ........................ 71 ultra low-power wake-up initialization ................... 133 unlock sequence .................................................... 128 code protection ............................................................... 250 comparator ...................................................................... 225 comparator voltage reference ....................................... 229 configuring .............................................................. 229 configuration bits ............................................................ 239 core features .................................................................... 13 cpu alu ............................................................................ 35 control registers ....................................................... 34 core registers ........................................................... 32 programmer?s model ................................................. 31
pic24fv32ka304 family ds39995b-page 314 ? 2011 microchip technology inc. crc registers .................................................................. 205 typical operation ..................................................... 205 user interface .......................................................... 204 data ................................................................. 204 data shift direction .......................................... 205 interrupt operation ........................................... 205 polynomial ....................................................... 204 ctmu measuring capacitance ........................................... 231 measuring time ....................................................... 233 pulse generation and delay .................................... 233 customer change notification service ............................ 317 customer notification service .......................................... 317 customer support ............................................................ 317 d data eeprom memory ..................................................... 67 erasing ....................................................................... 70 operations ................................................................. 69 programming bulk erase .......................................................... 71 reading data eeprom .................................... 72 single-word write .............................................. 71 programming control registers nvmadr(u) ...................................................... 69 nvmcon ........................................................... 67 nvmkey ............................................................ 67 data memory address space ........................................................... 39 memory map .............................................................. 39 near data space ....................................................... 40 organization ............................................................... 40 sfr space ................................................................. 40 software stack ........................................................... 53 space width ............................................................... 39 dc characteristics comparator .............................................................. 278 comparator voltage reference ............................... 278 ctmu current source ............................................. 279 data eeprom memory ........................................... 278 high/low-voltage detect ......................................... 266 i/o pin input specifications ...................................... 276 i/o pin output specifications ................................... 277 idle current (i idle ) ................................................... 269 internal voltage regulator specifications ................ 279 operating current (i dd ) ............................................ 267 power-down current (i pd ) ....................................... 271 program memory ..................................................... 277 temperature and voltage specifications ................. 265 development support ...................................................... 251 device features (summary) ........................................ 15, 16 e electrical characteristics absolute maximum ratings ..................................... 263 thermal operating conditions ................................. 265 thermal packaging characteristics ......................... 265 v/f graphs ............................................................... 264 equations baud rate reload calculation ................................. 175 calculating the pwm period .................................... 159 calculation for maximum pwm resolution .............. 159 device and spi clock speed relationship .............. 172 pwm period and duty cycle calculations ............... 159 uart baud rate with brgh = 0 ............................ 182 uart baud rate with brgh = 1 ............................ 182 errata ................................................................................. 11 examples baud rate error calculation (brgh = 0) ................ 182 f flash program memory control registers ....................................................... 60 enhanced icsp operation ........................................ 60 programming algorithm ............................................. 62 programming operations ........................................... 60 rtsp operation ........................................................ 60 table instructions ...................................................... 59 h high/low-voltage detect (hlvd) .................................... 209 i i/o ports analog port configuration ........................................ 140 analog selection registers ...................................... 140 input change notification ........................................ 142 open-drain configuration ........................................ 140 parallel (pio) ........................................................... 139 i 2 c clock rates ............................................................. 175 communicating as master in single master environment .................................................... 173 pin remapping options ........................................... 173 reserved addresses ............................................... 175 slave address masking ........................................... 175 in-circuit debugger .......................................................... 250 in-circuit serial programming (icsp) .............................. 250 input capture 32-bit mode ............................................................. 152 operations ............................................................... 152 synchronous and trigger modes ............................. 151 input capture with dedicated timers .............................. 151 instruction set opcode symbols ..................................................... 256 overview .................................................................. 257 summary ................................................................. 255 internet address .............................................................. 317 interrupts alternate interrupt vector table (aivt) ..................... 79 control and status registers ..................................... 82 implemented vectors ................................................. 81 interrupt vector table (ivt) ....................................... 79 reset sequence ........................................................ 79 setup procedures .................................................... 115 trap vectors .............................................................. 81 vector table .............................................................. 80 m microchip internet web site ............................................. 317 mplab asm30 assembler, linker, librarian .................. 252 mplab integrated development environment software .................................................................. 251 mplab pm3 device programmer ................................... 254 mplab real ice in-circuit emulator system ............... 253 mplink object linker/mplib object librarian ............... 252 n near data space ............................................................... 40
? 2011 microchip technology inc. ds39995b-page 315 pic24fv32ka304 family o on-chip voltage regulator .............................................. 248 oscillator configuration clock switching ........................................................ 123 sequence ......................................................... 123 configuration values for clock selection ................. 118 cpu clocking scheme ............................................ 118 initial configuration on por .................................... 118 reference clock output ........................................... 124 output compare 32-bit mode .............................................................. 155 operations ............................................................... 157 subcycle resolution ................................................ 160 synchronous and trigger modes ............................. 155 p packaging details ...................................................................... 292 marking .................................................................... 289 pinout descriptions ............................................................ 18 power-saving ................................................................... 137 power-saving features ................................................... 127 clock frequency, clock switching ........................... 127 coincident interrupts ................................................ 128 instruction-based modes ......................................... 127 deep sleep ...................................................... 128 idle ................................................................... 128 sleep ................................................................ 127 selective peripheral control .................................... 137 ultra low-power wake-up ....................................... 133 voltage regulator-based ......................................... 135 deep sleep mode ............................................ 135 fast wake-up sleep mode .............................. 135 retention sleep mode ..................................... 135 run mode ........................................................ 135 sleep (standby) mode ..................................... 135 product identification system .......................................... 319 program and data memory access using table instructions ................................ 55 program space visibility ............................................ 57 program and data memory spaces addressing ................................................................. 53 interfacing .................................................................. 53 program memory address space ........................................................... 37 device configuration words ...................................... 38 hard memory vectors ................................................ 38 memory map .............................................................. 37 organization ............................................................... 38 program verification ........................................................ 250 pulse-width modulation (pwm) mode ............................. 158 pulse-width modulation. see pwm. pwm duty cycle and period ............................................. 159 r reader response ............................................................ 318 register maps a/d converter (adc) ................................................. 49 analog select ............................................................. 50 clock control ............................................................. 51 cpu core ................................................................... 41 crc ........................................................................... 51 ctmu ......................................................................... 50 deep sleep ................................................................ 51 i 2 c ............................................................................. 46 icn ............................................................................ 42 input capture ............................................................. 44 interrupt controller ..................................................... 43 nvm ........................................................................... 52 output compare ........................................................ 45 pad configuration ...................................................... 48 pmd ........................................................................... 52 porta ...................................................................... 47 portb ...................................................................... 47 portc ...................................................................... 48 real-time clock and calendar (rtcc) .................... 50 spi ............................................................................. 47 timer ......................................................................... 44 uart ......................................................................... 46 ultra low-power wake-up ......................................... 52 registers ad1chith (a/d scan compare hit, high word) ...................................................... 220 ad1chith (a/d scan compare hit, low word) ..... 220 ad1chs (a/d sample select) ................................ 219 ad1con1 (a/d control 1) ....................................... 215 ad1con2 (a/d control 2) ....................................... 216 ad1con3 (a/d control 3) ....................................... 217 ad1con5 (a/d control 5) ....................................... 218 ad1ctmenh (ctmu enable, high word) ............. 222 ad1ctmenl (ctmu enable, low word) ............... 222 adcssh (a/d input scan select, high word) ........ 221 adcssl (a/d input scan select, low word) ......... 221 alcfgrpt (alarm configuration) .......................... 194 alminsec (alarm minutes and seconds value) .............................................................. 198 almthdy (alarm month and day value) ............... 197 alwdhr (alarm weekday and hours value) ........ 197 ansa (analog selection, porta) .......................... 140 ansb (analog selection, portb) .......................... 141 ansc (analog selection, portc) .......................... 141 clkdiv (clock divider) ........................................... 121 cmstat (comparator status) ................................ 228 cmxcon (comparator x control) ........................... 227 corcon (cpu control) ........................................... 35 corcon (cpu core control) .................................. 84 crccon1 (crc control 1) .................................... 206 crccon2 (crc control 2) .................................... 207 crcxorh (crc xor polynomial, high byte) ...... 208 crcxorl (crc xor polynomial, low byte) ........ 207 ctmucon (ctmu control 1) ................................. 234 ctmucon2 (ctmu control 2) ............................... 235 ctmuicon (ctmu current control) ...................... 237 cvrcon (comparator voltage reference control) .......................................... 230 devid (device id) ................................................... 246 devrev (device revision) ..................................... 247 dscon (deep sleep control) ................................. 131 dswake (deep sleep wake-up source) ............... 132 fbs (boot segment configuration) ......................... 239 fds (deep sleep configuration) ............................. 245 fgs (general segment configuration) ................... 240 ficd (in-circuit debugger configuration) ............... 244 fosc (oscillator configuration) .............................. 241 foscsel (oscillator selection configuration) ....... 240 fpor (reset configuration) ................................... 243 fwdt (watchdog timer configuration) .................. 242 hlvdcon (high/low-voltage detect control) ....... 210 i2cxmsk (i2cx slave mode address mask) ........... 180
pic24fv32ka304 family ds39995b-page 316 ? 2011 microchip technology inc. i2cxstat (i2cx status) .......................................... 178 i2cxxcon (i2cx control) ........................................ 176 icxcon1 (input capture x control 1) ...................... 153 icxcon2 (input capture x control 2) ...................... 154 iec0 (interrupt enable control 0) .............................. 93 iec1 (interrupt enable control 1) .............................. 94 iec2 (interrupt enable control 2) .............................. 95 iec3 (interrupt enable control 3) .............................. 96 iec4 (interrupt enable control 4) .............................. 97 iec5 (interrupt enable control 5) .............................. 98 ifs0 (interrupt flag status 0) .................................... 87 ifs1 (interrupt flag status 1) .................................... 88 ifs2 (interrupt flag status 2) .................................... 89 ifs3 (interrupt flag status 3) .................................... 90 ifs4 (interrupt flag status 4) .................................... 91 ifs5 (interrupt flag status 5) .................................... 92 intcon1 (interrupt control 1) ................................... 85 inttreg (interrupt control and status) .................. 114 ipc0 (interrupt priority control 0) .............................. 99 ipc1 (interrupt priority control 1) ............................ 100 ipc12 (interrupt priority control 12) ........................ 109 ipc120 (interrupt priority control 20) ...................... 113 ipc15 (interrupt priority control 15) ........................ 110 ipc16 (interrupt priority control 16) ........................ 111 ipc18 (interrupt priority control 18) ........................ 112 ipc2 (interrupt priority control 2) ............................ 101 ipc3 (interrupt priority control 3) ............................ 102 ipc4 (interrupt priority control 4) ............................ 103 ipc5 (interrupt priority control 5) ............................ 104 ipc6 (interrupt priority control 6) ............................ 105 ipc7 (interrupt priority control 7) ............................ 106 ipc8 (interrupt priority control 8) ............................ 107 ipc9 (interrupt priority control 9) ............................ 108 minsec (rtcc minutes and seconds value) ........ 196 mthdy (rtcc month and day value) ................... 195 nvmcon (flash memory control) ............................ 61 nvmcon (nonvolatile memory control) ................... 68 ocxcon1 (output compare x control 1) ............... 161 ocxcon2 (output compare x control 2) ............... 163 osccon (oscillator control) .... ................. ........ ..... 119 osctun (frc oscillator tune) .............................. 122 padcfg1 (pad configuration control) ................... 180 rcfgcal (rtcc calibration and configuration) .................................................. 191 rcon (reset control) ............................................... 74 refocon (reference oscillator control) ............... 125 rtccswt (control/sample window timer) ........... 199 rtcpwc (rtcc configuration 2) .......................... 193 spixcon1 (spix control 1) ..................................... 170 spixcon2 (spix control 2) ..................................... 171 spixstat (spix status and control) ...................... 168 sr (alu status) .............................................. 34, 83 t1con (timer1 control) .......................................... 144 txcon (timer2/4 control) ....................................... 148 tycon (timer3/5 control) ....................................... 149 ulpwcon (ulpwu control) .................................. 134 uxmode (uartx mode) ......................................... 184 uxrxreg (uartx receive) ................................... 188 uxsta (uartx status and control) ........................ 186 uxtxreg (uartx transmit) .................................. 188 wkdyhr (rtcc weekday and hours value) ........ 196 year (rtcc year value) ....................................... 195 resets brown-out reset (bor) ............................................. 77 clock source selection .............................................. 75 deep sleep bor (dsbor) ....................................... 77 delay times ............................................................... 76 device times ............................................................. 76 rcon flag operation ............................................... 75 sfr states ................................................................ 77 revision history ............................................................... 311 rtcc ............................................................................... 189 alarm configuration ................................................. 200 alarm mask settings (figure) ................................... 201 calibration ............................................................... 200 module registers ..................................................... 190 mapping ........................................................... 190 clock source selection ........................... 190 write lock ........................................................ 190 source clock ........................................................... 189 s serial peripheral interface. see spi. sfr space ........................................................................ 40 software simulator (mplab sim) ................................... 253 software stack ................................................................... 53 t timer1 .............................................................................. 143 timer2/3 ........................................................................... 145 timer2/3 and timer4/5 .................................................... 145 timing diagrams clko and i/o timing .............................................. 283 external clock .......................................................... 281 timing requirements clko and i/o .......................................................... 283 external clock .......................................................... 281 pll clock specifications ......................................... 282 u uart ............................................................................... 181 baud rate generator (brg) ................................... 182 break and sync transmit sequence ....................... 183 irda support ............................................................ 183 operation of uxcts and uxrts control pins ........ 183 receiving in 8-bit or 9-bit data mode ...................... 183 transmitting in 8-bit data mode .............................. 183 transmitting in 9-bit data mode .............................. 183 w watchdog timer deep sleep (dswdt) ............................................. 250 watchdog timer (wdt) ................................................... 248 windowed operation ............................................... 249 www address ................................................................ 317 www, on-line support .................................................... 11
? 2011 microchip technology inc. ds39995b-page 317 pic24fv32ka304 family the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
pic24fv32ka304 family ds39995b-page 318 ? 2011 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39995b pic24fv32ka304 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2011 microchip technology inc. ds39995b-page 319 pic24fv32ka304 family product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . architecture 24 = 16-bit modified harvard without dsp flash memory family f = standard voltage range flash program memory fv = wide voltage range flash program memory product group ka3 = general purpose microcontrollers pin count 01 = 20-pin 02 = 28-pin 04 = 44-pin temperature range i = -40 ? c to +85 ? c (industrial) package sp = spdip so = soic ss = ssop ml = qfn p=pdip pt = tqfp pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample examples: a) PIC24FV32KA304-I/ml: wide voltage range, general purpose, 32 -kbyte program memory, 44-pin, industrial temp, qfn package b) pic24f16ka302-i/ss: standard voltage range, general purpose, 16-kbyte program memory, 28-pin, industrial temp, ssop package microchip trademark architecture flash memory family program memory size (kb) product group pin count temperature range package pattern pic 24 f v 32 k a 3 04 t - i / pt - xxx tape and reel flag (if applicable)
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